Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * TX4939 internal IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Based on RBTX49xx patch from CELF patch archive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * (C) Copyright TOSHIBA CORPORATION 2005-2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MODNAME	"tx4939ide"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TX4939IDE_Data			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TX4939IDE_Error_Feature		0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TX4939IDE_Sec			0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TX4939IDE_LBA0			0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TX4939IDE_LBA1			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TX4939IDE_LBA2			0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TX4939IDE_DevHead		0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TX4939IDE_Stat_Cmd		0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TX4939IDE_AltStat_DevCtl	0x402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* H/W DMA Registers  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TX4939IDE_DMA_Cmd	0x800	/* 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TX4939IDE_DMA_Stat	0x802	/* 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TX4939IDE_PRD_Ptr	0x804	/* 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* ATA100 CORE Registers (16-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define TX4939IDE_Sys_Ctl	0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TX4939IDE_Xfer_Cnt_1	0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TX4939IDE_Xfer_Cnt_2	0xc0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TX4939IDE_Sec_Cnt	0xc10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TX4939IDE_Start_Lo_Addr	0xc18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TX4939IDE_Start_Up_Addr	0xc20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TX4939IDE_Add_Ctl	0xc28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TX4939IDE_Lo_Burst_Cnt	0xc30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TX4939IDE_Up_Burst_Cnt	0xc38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TX4939IDE_PIO_Addr	0xc88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TX4939IDE_H_Rst_Tim	0xc90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TX4939IDE_Int_Ctl	0xc98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TX4939IDE_Pkt_Cmd	0xcb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TX4939IDE_Bxfer_Cnt_Hi	0xcc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TX4939IDE_Bxfer_Cnt_Lo	0xcc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TX4939IDE_Dev_TErr	0xcd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TX4939IDE_Pkt_Xfer_Ctl	0xcd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TX4939IDE_Start_TAddr	0xce0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* bits for Int_Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TX4939IDE_INT_ADDRERR	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TX4939IDE_INT_REACHMUL	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TX4939IDE_INT_DEVTIMING	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TX4939IDE_INT_UDMATERM	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define TX4939IDE_INT_TIMER	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TX4939IDE_INT_BUSERR	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TX4939IDE_INT_XFEREND	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TX4939IDE_INT_HOST	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TX4939IDE_IGNORE_INTS	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define tx4939ide_swizzlel(a)	((a) ^ 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define tx4939ide_swizzlew(a)	((a) ^ 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define tx4939ide_swizzleb(a)	((a) ^ 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define tx4939ide_swizzlel(a)	(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define tx4939ide_swizzlew(a)	(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define tx4939ide_swizzleb(a)	(a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static u16 tx4939ide_readw(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return __raw_readw(base + tx4939ide_swizzlew(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static u8 tx4939ide_readb(void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return __raw_readb(base + tx4939ide_swizzleb(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	__raw_writel(val, base + tx4939ide_swizzlel(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	__raw_writew(val, base + tx4939ide_swizzlew(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	__raw_writeb(val, base + tx4939ide_swizzleb(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TX4939IDE_BASE(hwif)	((void __iomem *)(hwif)->extra_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int is_slave = drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u8 safe = pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ide_drive_t *pair;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (pair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * Update Command Transfer Mode for master/slave and Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * Transfer Mode for this drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mask = is_slave ? 0x07f00000 : 0x000007f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	hwif->select_data = (hwif->select_data & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	const u8 mode = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Update Data Transfer Mode for this drive. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (mode >= XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		val = mode - XFER_UDMA_0 + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		val = mode - XFER_MW_DMA_0 + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (drive->dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		mask = 0x00f00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		val <<= 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		mask = 0x000000f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		val <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	hwif->select_data = (hwif->select_data & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ctl & TX4939IDE_INT_BUSERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		/* reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ndelay(270);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (ctl & (TX4939IDE_INT_ADDRERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		   TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		pr_err("%s: Error interrupt %#x (%s%s%s )\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		       hwif->name, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		       ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		       ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		       ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void tx4939ide_clear_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	ide_hwif_t *hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	u16 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * for DMA case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (drive->waiting_for_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ctl = tx4939ide_check_error_ints(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		ATA_CBL_PATA40 : ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u8 unit = drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		dma_stat |= (1 << (5 + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dma_stat &= ~(1 << (5 + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define tx4939ide_dma_host_set	ide_dma_host_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static u8 tx4939ide_clear_dma_status(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u8 dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* read DMA status for INTR & ERROR flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* clear INTR & ERROR flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			 TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* recover intmask cleared by writing to bit2 of DMA_Stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* custom ide_build_dmatable to handle swapped layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u32 *table = (u32 *)hwif->dmatable_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	unsigned int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		u32 cur_addr, cur_len, bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		cur_addr = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		cur_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 * Fill in the DMA table, without crossing any 64kB boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		while (cur_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			if (count++ >= PRD_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				goto use_pio_instead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			bcount = 0x10000 - (cur_addr & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			if (bcount > cur_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				bcount = cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			 * This workaround for zero count seems required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			 * (standard ide_build_dmatable does it too)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			if (bcount == 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				bcount = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			*table++ = bcount & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			*table++ = cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			cur_addr += bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			cur_len -= bcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		*(table - 2) |= 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) use_pio_instead:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	printk(KERN_ERR "%s: %s\n", drive->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		count ? "DMA table too small" : "empty DMA table?");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	return 0; /* revert to PIO for this request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define tx4939ide_build_dmatable	ide_build_dmatable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* fall back to PIO! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (tx4939ide_build_dmatable(drive, cmd) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* PRD table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	/* specify r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* clear INTR & ERROR flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	tx4939ide_clear_dma_status(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int tx4939ide_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	u8 dma_stat, dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/* get DMA command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* stop DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	/* read and clear the INTR & ERROR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	dma_stat = tx4939ide_clear_dma_status(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* verify good DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if ((dma_stat & CHECK_DMA_MASK) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		/* INT_IDE lost... bug? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return ((dma_stat & CHECK_DMA_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* returns 1 if DMA IRQ issued, 0 otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int tx4939ide_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u16 ctl, ide_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	u8 dma_stat, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ctl = tx4939ide_check_error_ints(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	switch (ide_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	case TX4939IDE_INT_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		/* On error, XFEREND might not be asserted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			/* Wait for XFEREND (Mask HOST and unmask XFEREND) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			ctl &= ~TX4939IDE_INT_XFEREND << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		ctl |= ide_int << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		if (!(dma_stat & ATA_DMA_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			pr_warn("%s: weird interrupt status. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				"DMA_Stat %#02x int_ctl %#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 				hwif->name, dma_stat, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 * Do not clear XFEREND, HOST now.  They will be cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * clearing bit2 of DMA_Stat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ctl &= ~ide_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void tx4939ide_init_hwif(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	/* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	ndelay(450);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/* mask some interrupts and clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			 TX4939IDE_Int_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	hwif->dma_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	 * for big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	return ide_allocate_dma_engine(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	void __iomem *base = TX4939IDE_BASE(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	 * Fix ATA100 CORE System Control Register. (The write to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	 * Device/Head register may write wrong data to the System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 * Control Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 * While Sys_Ctl is written here, dev_select() is not needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			      u8 valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	ide_tf_load(drive, tf, valid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (valid & IDE_VALID_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		tx4939ide_tf_load_fixup(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* custom iops (independent from SWAP_IO_SPACE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 				void *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	unsigned long port = drive->hwif->io_ports.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	unsigned short *ptr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	unsigned int count = (len + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	while (count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		*ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 				void *buf, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	unsigned long port = drive->hwif->io_ports.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	unsigned short *ptr = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	unsigned int count = (len + 1) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		__raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct ide_tp_ops tx4939ide_tp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	.exec_command		= ide_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	.read_status		= ide_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.read_altstatus		= ide_read_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.write_devctl		= ide_write_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	.dev_select		= ide_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.tf_load		= tx4939ide_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.tf_read		= ide_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.input_data		= tx4939ide_input_data_swap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	.output_data		= tx4939ide_output_data_swap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #else	/* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct ide_tp_ops tx4939ide_tp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	.exec_command		= ide_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	.read_status		= ide_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	.read_altstatus		= ide_read_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	.write_devctl		= ide_write_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	.dev_select		= ide_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	.tf_load		= tx4939ide_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	.tf_read		= ide_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	.input_data		= ide_input_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	.output_data		= ide_output_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #endif	/* __LITTLE_ENDIAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct ide_port_ops tx4939ide_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	.set_pio_mode		= tx4939ide_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	.set_dma_mode		= tx4939ide_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	.clear_irq		= tx4939ide_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	.cable_detect		= tx4939ide_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct ide_dma_ops tx4939ide_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	.dma_host_set		= tx4939ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	.dma_setup		= tx4939ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	.dma_start		= ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	.dma_end		= tx4939ide_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	.dma_test_irq		= tx4939ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	.dma_lost_irq		= ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	.dma_sff_read_status	= tx4939ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct ide_port_info tx4939ide_port_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	.init_hwif		= tx4939ide_init_hwif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	.init_dma		= tx4939ide_init_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	.port_ops		= &tx4939ide_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	.dma_ops		= &tx4939ide_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	.tp_ops			= &tx4939ide_tp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	.host_flags		= IDE_HFLAG_MMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	.pio_mask		= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	.mwdma_mask		= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	.udma_mask		= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	.chipset		= ide_generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int __init tx4939ide_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	struct ide_hw hw, *hws[] = { &hw };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	struct ide_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	unsigned long mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	if (!devm_request_mem_region(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 				     resource_size(res), MODNAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 					      resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	if (!mapbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	memset(&hw, 0, sizeof(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	hw.io_ports.data_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	hw.io_ports.error_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 		mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	hw.io_ports.nsect_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 		mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	hw.io_ports.lbal_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	hw.io_ports.lbam_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	hw.io_ports.lbah_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	hw.io_ports.device_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	hw.io_ports.command_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 		mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	hw.io_ports.ctl_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	hw.irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	hw.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	/* use extra_base for base address of the all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	host->ports[0]->extra_base = mapbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	ret = ide_host_register(host, &tx4939ide_port_info, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		ide_host_free(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	platform_set_drvdata(pdev, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int __exit tx4939ide_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	struct ide_host *host = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	ide_host_remove(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int tx4939ide_resume(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 	struct ide_host *host = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 	ide_hwif_t *hwif = host->ports[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	tx4939ide_init_hwif(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define tx4939ide_resume	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct platform_driver tx4939ide_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 		.name = MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	.remove = __exit_p(tx4939ide_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	.resume = tx4939ide_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) module_platform_driver_probe(tx4939ide_driver, tx4939ide_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MODULE_DESCRIPTION("TX4939 internal IDE driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MODULE_ALIAS("platform:tx4939ide");