Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  Copyright (c) 1997-1998  Mark Lord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (c) 2007       MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  June 22, 2004 - get rid of check_region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *                   - Jesper Juhl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This module provides support for the bus-master IDE DMA function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * including a "Precision Instruments" board.  The TRM290 pre-dates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * the sff-8038 standard (ide-dma.c) by a few months, and differs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * significantly enough to warrant separate routines for some functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * while re-using others from ide-dma.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * EXPERIMENTAL!  It works for me (a sample of one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Works reliably for me in DMA mode (READs only),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * DMA WRITEs are disabled by default (see #define below);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * DMA is not enabled automatically for this chipset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * but can be turned on manually (with "hdparm -d1") at run time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * I need volunteers with "spare" drives for further testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * and development, and maybe to help figure out the peculiarities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * Even knowing the registers (below), some things behave strangely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TRM290_NO_DMA_WRITES	/* DMA writes seem unreliable sometimes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * TRM-290 PCI-IDE2 Bus Master Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * ================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * The configuration registers are addressed in normal I/O port space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * and are used as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * trm290_base depends on jumper settings, and is probed for by ide-dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *	bit7 must always be written as "1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *	bits6-2 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *	bit1 1=legacy_compatible_mode, 0=native_pci_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *	bit0 1=test_mode, 0=normal(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * trm290_base+2 when READ: status register (byte, read-only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *	bits7-2 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *	bit1 channel0 busmaster interrupt status 0=none, 1=asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  *	bit0 channel0 interrupt status 0=none, 1=asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * trm290_base+3 Interrupt mask register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  *	bits7-5 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *	bit4 legacy_header: 1=present, 0=absent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *	bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *	bit2 channel1 interrupt status 0=none, 1=asserted (read only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *	bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  *	bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * trm290_base+1 "CPR" Config Pointer Register (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *	bit7 1=autoincrement CPR bits 2-0 after each access of CDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *	bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *	bit5 0=enabled master burst access (default), 1=disable  (write only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	bit3 0=primary IDE channel, 1=secondary IDE channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	bits2-0 register index for accesses through CDR port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * trm290_base+0 "CDR" Config Data Register (word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	two sets of seven config registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *	selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *	each index defined below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * Index-0 Base address register for command block (word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *	defaults: 0x1f0 for primary, 0x170 for secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * Index-1 general config register (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *	bit7 1=DMA enable, 0=DMA disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *	bit6 1=activate IDE_RESET, 0=no action (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *	bit5 1=enable IORDY, 0=disable IORDY (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *	bit4 0=16-bit data port(default), 1=8-bit (XT) data port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *	bit3 interrupt polarity: 1=active_low, 0=active_high(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  *	bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *	bit1 bus_master_mode(?): 1=enable, 0=disable(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *	bit0 enable_io_ports: 1=enable(default), 0=disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *	bits7-0 bits7-0 of readahead count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * Index-3 read-ahead config register (byte, write only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  *	bit7 1=enable_readahead, 0=disable_readahead(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  *	bit6 1=clear_FIFO, 0=no_action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *	bit5 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *	bit4 mode4 timing control: 1=enable, 0=disable(default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *	bit3 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *	bit2 undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	bits1-0 bits9-8 of read-ahead count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * Index-4 base address register for control block (word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *	defaults: 0x3f6 for primary, 0x376 for secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * Index-5 data port timings (shared by both drives) (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  *	standard PCI "clk" (clock) counts, default value = 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  *	bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  *	bits5-3 hold time:	000=1clk, 001=2clk, 010=3clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  *				011=4clk, 100=5clk, 101=6clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  *				110=8clk, 111=12clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  *	bits2-0 active time:	000=2clk, 001=3clk, 010=4clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  *				011=5clk, 100=6clk, 101=8clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *				110=12clk, 111=16clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  * Index-6 command/control port timings (shared by both drives) (byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *	same layout as Index-5, default value = 0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * Suggested CDR programming for PIO mode0 (600ns):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  *	0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde	; primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde	; secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * Suggested CDR programming for PIO mode3 (180ns):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde	; primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *	0x0170,0x21,0xff,0x80,0x0376,0x09,0xde	; secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * Suggested CDR programming for PIO mode4 (120ns):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *	0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde	; primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  *	0x0170,0x21,0xff,0x80,0x0376,0x00,0xde	; secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define DRV_NAME "trm290"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u16 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* select PIO or DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (reg != hwif->select_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		hwif->select_data = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		/* set PIO/DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		outw(reg & 0xff, hwif->config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* enable IRQ if not probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (drive->dev_flags & IDE_DFLAG_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		reg = inw(hwif->config_data + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		reg &= 0x13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		reg &= ~(1 << hwif->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		outw(reg, hwif->config_data + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void trm290_dev_select(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int trm290_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (cmd->tf_flags & IDE_TFLAG_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef TRM290_NO_DMA_WRITES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* always use PIO for writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int trm290_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	unsigned int count, rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	count = ide_build_dmatable(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		/* try PIO instead of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	outl(hwif->dmatable_dma | rw, hwif->dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	outw(count * 2 - 1, hwif->dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void trm290_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	trm290_prepare_drive(drive, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int trm290_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u16 status = inw(drive->hwif->dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	trm290_prepare_drive(drive, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return status != 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int trm290_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u16 status = inw(drive->hwif->dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return status == 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void trm290_dma_host_set(ide_drive_t *drive, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void init_hwif_trm290(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	unsigned int  cfg_base	= pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if ((dev->class & 5) && cfg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		cfg_base = 0x3df0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	hwif->config_data = cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	       hwif->name, hwif->dma_base, hwif->dma_base + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (ide_allocate_dma_engine(hwif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* put config reg into first byte of hwif->select_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* select PIO as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	hwif->select_data = 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	outb(hwif->select_data, hwif->config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* get IRQ info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	reg = inb(hwif->config_data + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* mask IRQs for both ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	reg = (reg & 0x10) | 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	outb(reg, hwif->config_data + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (reg & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		/* legacy mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		hwif->irq = hwif->channel ? 15 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * My trm290-based card doesn't seem to work with all possible values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * for the control basereg, so this kludge ensures that we use only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * values that are known to work.  Ugh.		-ml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		static u16 next_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		u8 old_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		old = inw(hwif->config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		old &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		old_mask = inb(old + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (old != compat && old_mask == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			/* leave lower 10 bits untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			compat += (next_offset += 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			hwif->io_ports.ctl_addr = compat + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			outw(compat | 1, hwif->config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			new = inw(hwif->config_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			printk(KERN_INFO "%s: control basereg workaround: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				"old=0x%04x, new=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				hwif->name, old, new & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct ide_tp_ops trm290_tp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.exec_command		= ide_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.read_status		= ide_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.read_altstatus		= ide_read_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.write_devctl		= ide_write_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.dev_select		= trm290_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.tf_load		= ide_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.tf_read		= ide_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.input_data		= ide_input_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.output_data		= ide_output_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct ide_dma_ops trm290_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.dma_host_set		= trm290_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.dma_setup 		= trm290_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.dma_start 		= trm290_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.dma_end		= trm290_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.dma_test_irq		= trm290_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.dma_lost_irq		= ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.dma_check		= trm290_dma_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct ide_port_info trm290_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.init_hwif	= init_hwif_trm290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.tp_ops 	= &trm290_tp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.dma_ops	= &trm290_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.host_flags	= IDE_HFLAG_TRM290 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			  IDE_HFLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #if 0 /* play it safe for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			  IDE_HFLAG_TRUST_BIOS_FOR_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			  IDE_HFLAG_NO_AUTODMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			  IDE_HFLAG_NO_LBA48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return ide_pci_init_one(dev, &trm290_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct pci_device_id trm290_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{ PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct pci_driver trm290_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.name		= "TRM290_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.id_table	= trm290_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	.probe		= trm290_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int __init trm290_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	return ide_pci_register_driver(&trm290_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void __exit trm290_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pci_unregister_driver(&trm290_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) module_init(trm290_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) module_exit(trm290_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_AUTHOR("Mark Lord");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MODULE_LICENSE("GPL");