Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SL82C105/Winbond 553 IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Maintainer unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Drive tuning added from Rebel.com's kernel sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  -- Russell King (15/11/98) linux@arm.linux.org.uk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Merge in Russell's HW workarounds, fix various problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * with the timing registers setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DRV_NAME "sl82c105"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * SL82C105 PCI config register 0x40 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CTRL_IDE_IRQB   (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CTRL_IDE_IRQA   (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CTRL_LEGIRQ     (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CTRL_P1F16      (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CTRL_P1EN       (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CTRL_P0F16      (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CTRL_P0EN       (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * Convert a PIO mode and cycle time to the required on/off times
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * for the interface.  This has protection against runaway timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int cmd_on, cmd_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u8 iordy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	cmd_on  = (t->active + 29) / 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (cmd_on == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		cmd_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (cmd_off == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		cmd_off = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (ide_pio_need_iordy(drive, pio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		iordy = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * Configure the chipset for PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static void sl82c105_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned long timings	= (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int reg			= 0x44 + drive->dn * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u16 drv_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	const u8 pio		= drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	drv_ctrl = get_pio_timings(drive, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * Store the PIO timings so that we can restore them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * in case DMA will be turned off...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	timings &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	timings |= drv_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	ide_set_drivedata(drive, (void *)timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	pci_write_config_word(dev, reg,  drv_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	pci_read_config_word (dev, reg, &drv_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			  ide_xfer_verbose(pio + XFER_PIO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			  ide_pio_cycle_time(drive, pio), drv_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Configure the chipset for DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void sl82c105_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u16 drv_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 * Store the DMA timings so that we can actually program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * them when DMA will be turned on...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	timings &= 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	timings |= (unsigned long)drv_ctrl << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	ide_set_drivedata(drive, (void *)timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int sl82c105_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	pci_read_config_dword(dev, 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return (val & mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * The SL82C105 holds off all IDE interrupts while in DMA mode until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * all DMA activity is completed.  Sometimes this causes problems (eg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * when the drive wants to report an error condition).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  * 0x7e is a "chip testing" register.  Bit 2 resets the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * state machine.  We need to kick this to work around various bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void sl82c105_reset_host(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	pci_read_config_word(dev, 0x7e, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	pci_write_config_word(dev, 0x7e, val | (1 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * If we get an IRQ timeout, it might be that the DMA state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * got confused.  Fix from Todd Inglett.  Details from Winbond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * This function is called when the IDE timer expires, the drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * indicates that it is READY, and we were waiting for DMA to complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void sl82c105_dma_lost_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ide_hwif_t *hwif	= drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u32 val, mask		= hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	u8 dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	printk(KERN_WARNING "sl82c105: lost IRQ, resetting host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	 * Check the raw interrupt from the drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	pci_read_config_dword(dev, 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		printk(KERN_INFO "sl82c105: drive was requesting IRQ, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		       "but host lost it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * Was DMA enabled?  If so, disable it - we're resetting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * host.  The IDE layer will be handling the drive for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (dma_cmd & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		printk(KERN_INFO "sl82c105: DMA was enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	sl82c105_reset_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * Winbond recommend that the DMA state machine is reset prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * setting the bus master DMA enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * The generic IDE core will have disabled the BMEN bit before this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  * function is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void sl82c105_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ide_hwif_t *hwif	= drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int reg 		= 0x44 + drive->dn * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	pci_write_config_word(dev, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			      (unsigned long)ide_get_drivedata(drive) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	sl82c105_reset_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void sl82c105_dma_clear(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	sl82c105_reset_host(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int sl82c105_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct pci_dev *dev	= to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	int reg 		= 0x44 + drive->dn * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int ret			= ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	pci_write_config_word(dev, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			      (unsigned long)ide_get_drivedata(drive));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * ATA reset will clear the 16 bits mode in the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * register, we need to reprogram it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void sl82c105_resetproc(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	pci_read_config_dword(dev, 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	val |= (CTRL_P1F16 | CTRL_P0F16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	pci_write_config_dword(dev, 0x40, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * Return the revision of the Winbond bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * which this function is part of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static u8 sl82c105_bridge_revision(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * The bridge should be part of the same device, but function 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 					dev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 					PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * Make sure it is a Winbond 553 and is an ISA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	    	pci_dev_put(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * We need to find function 0's revision, not function 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	pci_dev_put(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return bridge->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * Enable the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * --BenH: It's arch fixup code that should enable channels that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * have not been enabled by firmware. I decided we can still enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * channel 0 here at least, but channel 1 has to be enabled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * firmware or arch code. We still set both to 16 bits mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int init_chipset_sl82c105(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pci_read_config_dword(dev, 0x40, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	pci_write_config_dword(dev, 0x40, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct ide_port_ops sl82c105_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.set_pio_mode		= sl82c105_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.set_dma_mode		= sl82c105_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.resetproc		= sl82c105_resetproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.test_irq		= sl82c105_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct ide_dma_ops sl82c105_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.dma_host_set		= ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.dma_setup		= ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.dma_start		= sl82c105_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.dma_end		= sl82c105_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.dma_test_irq		= ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.dma_lost_irq		= sl82c105_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.dma_clear		= sl82c105_dma_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.dma_sff_read_status	= ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct ide_port_info sl82c105_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.init_chipset	= init_chipset_sl82c105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.enablebits	= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.port_ops	= &sl82c105_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.dma_ops	= &sl82c105_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.host_flags	= IDE_HFLAG_IO_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			  IDE_HFLAG_UNMASK_IRQS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			  IDE_HFLAG_SERIALIZE_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			  IDE_HFLAG_NO_AUTODMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.pio_mask	= ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct ide_port_info d = sl82c105_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	u8 rev = sl82c105_bridge_revision(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (rev <= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		 * Never ever EVER under any circumstances enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		 * DMA when the bridge is this old.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				 "revision %d, BM-DMA disabled\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		d.dma_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		d.mwdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct pci_device_id sl82c105_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct pci_driver sl82c105_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.name		= "W82C105_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.id_table	= sl82c105_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.probe		= sl82c105_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int __init sl82c105_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return ide_pci_register_driver(&sl82c105_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void __exit sl82c105_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	pci_unregister_driver(&sl82c105_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_init(sl82c105_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) module_exit(sl82c105_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_LICENSE("GPL");