^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Thanks :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SiS Taiwan : for direct support and hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Daniela Engert : for initial ATA100 advices and numerous others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * for checking code correctness, providing patches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Original tests and design on the SiS620 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ATA100 tests and design on the SiS735 chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ATA16/33 support from specs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * SiS chipset documentation available under NDA to companies only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * (not to individuals).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * can figure out that we have a more modern and more capable 5513 by looking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * for the respective NorthBridge IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * bits, changing its device id to the true one - 5517 for 961 and 5518 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 962/963.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DRV_NAME "sis5513"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* registers layout and init values are chipset family dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #undef ATA_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ATA_16 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ATA_33 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ATA_66 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ATA_100 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ATA_133a 0x06 /* SiS961b with 133 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ATA_133 0x07 /* SiS962/963 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u8 chipset_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Devices supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u16 host_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 chipset_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } SiSHostChipInfo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Cycle time bits and values vary across chip dma capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) These three arrays hold the register layout and the values to set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) different cycle_time range and offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) See SiS962 data sheet for more detail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 2, 1, 1, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 4, 3, 2, 1, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 4, 3, 2, 1, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 6, 4, 3, 1, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 9, 6, 4, 2, 2, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 9, 6, 4, 2, 2, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Initialize time, Active time, Recovery time vary across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IDE clock settings. These 3 arrays hold the register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static u8 ini_time_value[][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 2, 1, 0, 0, 0, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 4, 3, 1, 1, 1, 3, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 4, 3, 1, 1, 1, 3, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 6, 4, 2, 2, 2, 4, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 9, 6, 3, 3, 3, 6, 3, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 9, 6, 3, 3, 3, 6, 3, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static u8 act_time_value[][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 9, 9, 9, 2, 2, 7, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 19, 19, 19, 5, 4, 14, 5, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 19, 19, 19, 5, 4, 14, 5, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 28, 28, 28, 7, 6, 21, 7, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 38, 38, 38, 10, 9, 28, 10, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 38, 38, 38, 10, 9, 28, 10, 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static u8 rco_time_value[][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 9, 2, 0, 2, 0, 7, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 19, 5, 1, 5, 2, 16, 3, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 19, 5, 1, 5, 2, 16, 3, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 30, 9, 3, 9, 4, 25, 6, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 40, 12, 4, 12, 5, 34, 12, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 40, 12, 4, 12, 5, 34, 12, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Printing configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Used for chipset type printing at boot time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static char *chipset_capability[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "ATA", "ATA 16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "ATA 33", "ATA 66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Configuration functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static u8 sis_ata133_get_base(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 reg54 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pci_read_config_dword(dev, 0x54, ®54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u16 t1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 drive_pci = 0x40 + drive->dn * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_read_config_word(dev, drive_pci, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* clear active/recovery timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) t1 &= ~0x070f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (mode >= XFER_MW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (chipset_family > ATA_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) t1 &= ~0x8000; /* disable UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) t1 |= pio_timings[mode - XFER_PIO_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_write_config_word(dev, drive_pci, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 t1, drive_pci = 0x40 + drive->dn * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* timing bits: 7:4 active 3:0 recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (mode >= XFER_MW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 t2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_read_config_byte(dev, drive_pci, &t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) t2 &= ~0x80; /* disable UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pci_write_config_byte(dev, drive_pci, t2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) t1 = mwdma_timings[mode - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) t1 = pio_timings[mode - XFER_PIO_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pci_write_config_byte(dev, drive_pci + 1, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 t1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pci_read_config_dword(dev, drive_pci, &t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) t1 &= 0xc0c00fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk = (t1 & 0x08) ? ATA_133 : ATA_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (mode >= XFER_MW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) t1 &= ~0x04; /* disable UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) idx = mode - XFER_MW_DMA_0 + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) idx = mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) t1 |= ini_time_value[clk][idx] << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) t1 |= act_time_value[clk][idx] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) t1 |= rco_time_value[clk][idx] << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pci_write_config_dword(dev, drive_pci, t1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void sis_program_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sis_ata16_program_timings(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else if (chipset_family < ATA_133) /* ATA_100/133a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sis_ata100_program_timings(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else /* ATA_133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sis_ata133_program_timings(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void config_drive_art_rwp(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 reg4bh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 rw_prefetch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pci_read_config_byte(dev, 0x4b, ®4bh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rw_prefetch = reg4bh & ~(0x11 << drive->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (drive->media == ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rw_prefetch |= 0x11 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (reg4bh != rw_prefetch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pci_write_config_byte(dev, 0x4b, rw_prefetch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void sis_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) config_drive_art_rwp(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sis_program_timings(drive, drive->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 regdw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pci_read_config_dword(dev, drive_pci, ®dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regdw |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regdw &= 0xfffff00f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* check if ATA133 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clk = (regdw & 0x08) ? ATA_133 : ATA_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) idx = mode - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regdw |= cycle_time_value[clk][idx] << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) regdw |= cvs_time_value[clk][idx] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_write_config_dword(dev, drive_pci, regdw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pci_read_config_byte(dev, drive_pci + 1, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* force the UDMA bit on if we want to use UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) reg |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* clean reg cycle time bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* set reg cycle time bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pci_write_config_byte(dev, drive_pci + 1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (chipset_family >= ATA_133) /* ATA_133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) sis_ata133_program_udma_timings(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else /* ATA_33/66/100a/100/133a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) sis_ata33_program_udma_timings(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void sis_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (speed >= XFER_UDMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sis_program_udma_timings(drive, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) sis_program_timings(drive, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static u8 sis_ata133_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 regdw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 drive_pci = sis_ata133_get_base(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pci_read_config_dword(dev, drive_pci, ®dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* if ATA133 disable, we should not set speed above UDMA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int sis_find_family(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct pci_dev *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) chipset_family = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) chipset_family = SiSHostChipInfo[i].chipset_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Special case for SiS630 : 630S/ET is ATA_100a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (host->revision >= 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) chipset_family = ATA_100a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pci_dev_put(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) printk(KERN_INFO DRV_NAME " %s: %s %s controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pci_name(dev), SiSHostChipInfo[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) chipset_capability[chipset_family]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!chipset_family) { /* Belongs to pci-quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 idemisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 trueid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Disable ID masking and register remapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_read_config_dword(dev, 0x54, &idemisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_write_config_dword(dev, 0x54, idemisc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (trueid == 0x5518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) printk(KERN_INFO DRV_NAME " %s: SiS 962/963 MuTIOL IDE UDMA133 controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) chipset_family = ATA_133;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Check for 5513 compatibility mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * We must use this, else the port enabled code will fail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * as it expects the enablebits at 0x4a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if ((idemisc & 0x40000000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) printk(KERN_INFO DRV_NAME " %s: Switching to 5513 register mapping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!chipset_family) { /* Belongs to pci-quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct pci_dev *lpc_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 trueid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 prefctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u8 idecfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pci_read_config_byte(dev, 0x4a, &idecfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pci_write_config_byte(dev, 0x4a, idecfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (trueid == 0x5517) { /* SiS 961/961B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pci_read_config_byte(dev, 0x49, &prefctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_dev_put(lpc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) printk(KERN_INFO DRV_NAME " %s: SiS 961B MuTIOL IDE UDMA133 controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) chipset_family = ATA_133a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) printk(KERN_INFO DRV_NAME " %s: SiS 961 MuTIOL IDE UDMA100 controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) chipset_family = ATA_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return chipset_family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int init_chipset_sis5513(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Make general config ops here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 1/ tell IDE channels to operate in Compatibility mode only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 2/ tell old chips to allow per drive IDE timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 regw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (chipset_family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case ATA_133:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* SiS962 operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci_read_config_word(dev, 0x50, ®w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (regw & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pci_write_config_word(dev, 0x50, regw&0xfff7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pci_read_config_word(dev, 0x52, ®w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (regw & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pci_write_config_word(dev, 0x52, regw&0xfff7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case ATA_133a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case ATA_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Fixup latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Set compatibility bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_read_config_byte(dev, 0x49, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!(reg & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_write_config_byte(dev, 0x49, reg|0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case ATA_100a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case ATA_66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Fixup latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* On ATA_66 chips the bit was elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pci_read_config_byte(dev, 0x52, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!(reg & 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pci_write_config_byte(dev, 0x52, reg|0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case ATA_33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* On ATA_33 we didn't have a single bit to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pci_read_config_byte(dev, 0x09, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((reg & 0x0f) != 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_write_config_byte(dev, 0x09, reg&0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case ATA_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* force per drive recovery and active timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) needed on ATA_33 and below chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pci_read_config_byte(dev, 0x52, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!(reg & 0x08))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pci_write_config_byte(dev, 0x52, reg|0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct sis_laptop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u16 subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct sis_laptop sis_laptop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* devid, subvendor, subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static u8 sis_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct sis_laptop *lap = &sis_laptop[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 ata66 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) while (lap->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (lap->device == pdev->device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) lap->subvendor == pdev->subsystem_vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) lap->subdevice == pdev->subsystem_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) lap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (chipset_family >= ATA_133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u16 regw = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u16 reg_addr = hwif->channel ? 0x52: 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pci_read_config_word(pdev, reg_addr, ®w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ata66 = (regw & 0x8000) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } else if (chipset_family >= ATA_66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u8 reg48h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u8 mask = hwif->channel ? 0x20 : 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pci_read_config_byte(pdev, 0x48, ®48h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ata66 = (reg48h & mask) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const struct ide_port_ops sis_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .set_pio_mode = sis_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .set_dma_mode = sis_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .cable_detect = sis_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct ide_port_ops sis_ata133_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .set_pio_mode = sis_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .set_dma_mode = sis_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .udma_filter = sis_ata133_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .cable_detect = sis_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct ide_port_info sis5513_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .init_chipset = init_chipset_sis5513,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .host_flags = IDE_HFLAG_NO_AUTODMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct ide_port_info d = sis5513_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rc = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (sis_find_family(dev) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (chipset_family >= ATA_133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) d.port_ops = &sis_ata133_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) d.port_ops = &sis_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) d.udma_mask = udma_rates[chipset_family];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void sis5513_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const struct pci_device_id sis5513_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static struct pci_driver sis5513_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .name = "SIS_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .id_table = sis5513_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .probe = sis5513_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .remove = sis5513_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int __init sis5513_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ide_pci_register_driver(&sis5513_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static void __exit sis5513_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pci_unregister_driver(&sis5513_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) module_init(sis5513_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) module_exit(sis5513_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DESCRIPTION("PCI driver module for SIS IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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