^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2003 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2008 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Documentation for CMD680:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Documentation for SiI 3112:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Errata and other documentation only available under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * FAQ Items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * If you are using Marvell SATA-IDE adapters with Maxtor drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * ensure the system is set up for ATA100/UDMA5, not UDMA6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * If you are using WD drives with SATA bridges you must set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * drive to "Single". "Master" will hang.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * If you have strange problems with nVidia chipset systems please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * see the SI support documentation and update your system BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The Dell DRAC4 has some interesting features including effectively hot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * unplugging/replugging the virtual CD interface when the DRAC is reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * This often causes drivers/ide/siimage to panic but is ok with the rather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * smarter code in libata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - VDMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRV_NAME "siimage"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * pdev_is_sata - check if device is SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @pdev: PCI device to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Returns true if this is a SATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int pdev_is_sata(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case PCI_DEVICE_ID_SII_3112:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case PCI_DEVICE_ID_SII_1210SA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) case PCI_DEVICE_ID_SII_680:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * is_sata - check if hwif is SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @hwif: interface to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Returns true if this is a SATA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline int is_sata(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return pdev_is_sata(to_pci_dev(hwif->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * siimage_selreg - return register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @hwif: interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @r: config offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Turn a config register offset into the right address in either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * PCI space or MMIO space to access the control register in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Thankfully this is a configuration operation, so isn't performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) base += 0xA0 + r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (hwif->host_flags & IDE_HFLAG_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) base += hwif->channel << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) base += hwif->channel << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * siimage_seldev - return register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @hwif: interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @r: config offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Turn a config register offset into the right address in either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * PCI space or MMIO space to access the control register in question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * including accounting for the unit shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) base += 0xA0 + r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (hwif->host_flags & IDE_HFLAG_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) base += hwif->channel << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) base += hwif->channel << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) base |= unit << unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tmp = readb((void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_read_config_byte(dev, addr, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tmp = readw((void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pci_read_config_word(dev, addr, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writeb(val, (void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pci_write_config_byte(dev, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) writew(val, (void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pci_write_config_word(dev, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(val, (void __iomem *)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pci_write_config_dword(dev, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * sil_udma_filter - compute UDMA mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @drive: IDE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Compute the available UDMA speeds for the device on the interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * For the CMD680 this depends on the clocking mode (scsc), for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * SI3112 SATA controller life is a bit simpler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static u8 sil_pata_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 scsc, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) scsc = sil_ioread8(dev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) switch (scsc & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) case 0x10: /* 133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) case 0x20: /* 2xPCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case 0x00: /* 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mask = ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) default: /* Disabled ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u8 sil_sata_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) char *m = (char *)&drive->id[ATA_ID_PROD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * sil_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Load the timing settings for this device mode into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void sil_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 speedt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u16 speedp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long addr = siimage_seldev(drive, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long tfaddr = siimage_selreg(hwif, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 tf_pio = pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) : (mmio ? 0xB4 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* trim *taskfile* PIO to the slowest of the master/slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 pair_pio = pair->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (pair_pio < tf_pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tf_pio = pair_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* cheat for now and use the docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) speedp = data_speed[pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) speedt = tf_speed[tf_pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sil_iowrite16(dev, speedp, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sil_iowrite16(dev, speedt, tfaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* now set up IORDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) speedp = sil_ioread16(dev, tfaddr - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) speedp &= ~0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mode = sil_ioread8(dev, base + addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mode &= ~(unit ? 0x30 : 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ide_pio_need_iordy(drive, pio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) speedp |= 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mode |= unit ? 0x10 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) sil_iowrite16(dev, speedp, tfaddr - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) sil_iowrite8(dev, mode, base + addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * sil_set_dma_mode - set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Tune the SiI chipset for the desired DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void sil_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 ultra = 0, multi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 mode = 0, unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) : (mmio ? 0xB4 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long ma = siimage_seldev(drive, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long ua = siimage_seldev(drive, 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mode = sil_ioread8 (dev, base + addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) multi = sil_ioread16(dev, ma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ultra = sil_ioread16(dev, ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) mode &= ~(unit ? 0x30 : 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ultra &= ~0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) scsc = is_sata(hwif) ? 1 : scsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) multi = dma[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ultra5[speed - XFER_UDMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mode |= unit ? 0x30 : 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) multi = dma[speed - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mode |= unit ? 0x20 : 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sil_iowrite8 (dev, mode, base + addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sil_iowrite16(dev, multi, ma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) sil_iowrite16(dev, ultra, ua);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int sil_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long addr = siimage_selreg(hwif, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 val = sil_ioread8(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Return 1 if INTRQ asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return (val & 8) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * siimage_mmio_dma_test_irq - check we caused an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @drive: drive we are testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Check if we caused an IDE DMA interrupt. We may also have caused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * SATA status interrupts, if so we clean them up and continue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void __iomem *sata_error_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (sata_error_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long base = (unsigned long)hwif->hwif_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 ext_stat = readl((void __iomem *)(base + 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 watchdog = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 sata_error = readl(sata_error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) writel(sata_error, sata_error_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) watchdog = (sata_error & 0x00680000) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printk(KERN_WARNING "%s: sata_error = 0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "watchdog = %d, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) drive->name, sata_error, watchdog, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) watchdog = (ext_stat & 0x8000) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ext_stat >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!(ext_stat & 0x0404) && !watchdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* return 1 if INTR asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int siimage_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return siimage_mmio_dma_test_irq(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ide_dma_test_irq(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * sil_sata_reset_poll - wait for SATA reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * @drive: drive we are resetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Poll the SATA phy and see whether it has come back from the dead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static blk_status_t sil_sata_reset_poll(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void __iomem *sata_status_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (sata_status_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* SATA Status is available only when in MMIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 sata_stat = readl(sata_status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if ((sata_stat & 0x03) != 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) hwif->name, sata_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return BLK_STS_IOERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return BLK_STS_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * sil_sata_pre_reset - reset hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @drive: IDE device being reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * For the SATA devices we need to handle recalibration/geometry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static void sil_sata_pre_reset(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (drive->media == ide_disk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) drive->special_flags &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * init_chipset_siimage - set up an SI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Perform the initial PCI set up for this device. Attempt to switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * to 133 MHz clocking if the system isn't already set up to do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int init_chipset_siimage(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void __iomem *ioaddr = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned long base, scsc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 rev = dev->revision, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) base = (unsigned long)ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ioaddr && pdev_is_sata(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 tmp32, irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* make sure IDE0/1 interrupts are not masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) irq_mask = (1 << 22) | (1 << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tmp32 = readl(ioaddr + 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (tmp32 & irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tmp32 &= ~irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) writel(tmp32, ioaddr + 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) readl(ioaddr + 0x48); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) writel(0, ioaddr + 0x148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) writel(0, ioaddr + 0x1C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) scsc_addr = base ? (base + 0x4A) : 0x8A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tmp = sil_ioread8(dev, scsc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) switch (tmp & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* On 100 MHz clocking, try and switch to 133 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sil_iowrite8(dev, tmp | 0x10, scsc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case 0x30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Clocking is disabled, attempt to force 133MHz clocking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* On 133Mhz clocking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* On PCIx2 clocking. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) tmp = sil_ioread8(dev, scsc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) sil_iowrite8 (dev, 0x72, base + 0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) sil_iowrite16(dev, 0x328A, base + 0xA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) sil_iowrite32(dev, 0x43924392, base + 0xA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sil_iowrite32(dev, 0x40094009, base + 0xAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (base && pdev_is_sata(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel(0xFFFF0000, ioaddr + 0x108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writel(0xFFFF0000, ioaddr + 0x188);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) writel(0x00680000, ioaddr + 0x148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) writel(0x00680000, ioaddr + 0x1C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* report the clocking mode of the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!pdev_is_sata(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const char *clk_str[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) tmp >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pci_name(dev), clk_str[tmp & 3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * init_mmio_iops_siimage - set up the iops for MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @hwif: interface to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * The basic setup here is fairly simple, we can use standard MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * operations. However we do have to set the taskfile register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * by hand as there isn't a standard defined layout for them this time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * The hardware supports buffered taskfiles and also some rather nice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * extended PRD tables. For better SI3112 support use the libata driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void init_mmio_iops_siimage(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) void *addr = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u8 ch = hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ide_io_ports *io_ports = &hwif->io_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Fill in the basic hwif bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hwif->host_flags |= IDE_HFLAG_MMIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hwif->hwif_data = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Now set up the hw. We have to do this ourselves as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * MMIO layout isn't the same as the standard port based I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) memset(io_ports, 0, sizeof(*io_ports));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) base = (unsigned long)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) base += 0xC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) base += 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * The buffered task file doesn't have status/control, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * can't currently use it sanely since we want to use LBA48 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) io_ports->data_addr = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) io_ports->error_addr = base + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) io_ports->nsect_addr = base + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) io_ports->lbal_addr = base + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) io_ports->lbam_addr = base + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) io_ports->lbah_addr = base + 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) io_ports->device_addr = base + 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) io_ports->status_addr = base + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) io_ports->ctl_addr = base + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (pdev_is_sata(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) base = (unsigned long)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) base += 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) hwif->irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int is_dev_seagate_sata(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const char *s = (const char *)&drive->id[ATA_ID_PROD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned len = strnlen(s, ATA_ID_PROD_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if ((len > 4) && (!memcmp(s, "ST", 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if ((!memcmp(s + len - 2, "AS", 2)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) (!memcmp(s + len - 3, "ASL", 3))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) printk(KERN_INFO "%s: applying pessimistic Seagate "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "errata fix\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * sil_quirkproc - post probe fixups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Called after drive probe we use this to decide whether the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Seagate fixup must be applied. This used to be in init_iops but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * that can occur before we know what drives are present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static void sil_quirkproc(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Try and rise the rqsize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) hwif->rqsize = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * init_iops_siimage - set up iops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @hwif: interface to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * Do the basic setup for the SIIMAGE hardware interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * and then do the MMIO setup if we can. This is the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * look in we get for setting up the hwif so that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * can get the iops right before using them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void init_iops_siimage(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct ide_host *host = dev_get_drvdata(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) hwif->hwif_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Pessimal until we finish probing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hwif->rqsize = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (host->host_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) init_mmio_iops_siimage(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * sil_cable_detect - cable detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @hwif: interface to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Check for the presence of an ATA66 capable cable on the interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static u8 sil_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned long addr = siimage_selreg(hwif, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 ata66 = sil_ioread8(dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const struct ide_port_ops sil_pata_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .set_pio_mode = sil_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .set_dma_mode = sil_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .quirkproc = sil_quirkproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .test_irq = sil_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .udma_filter = sil_pata_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .cable_detect = sil_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const struct ide_port_ops sil_sata_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .set_pio_mode = sil_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .set_dma_mode = sil_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .reset_poll = sil_sata_reset_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .pre_reset = sil_sata_pre_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .quirkproc = sil_quirkproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .test_irq = sil_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .udma_filter = sil_sata_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .cable_detect = sil_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct ide_dma_ops sil_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .dma_start = ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .dma_end = ide_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .dma_test_irq = siimage_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define DECLARE_SII_DEV(p_ops) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .name = DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .init_chipset = init_chipset_siimage, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .init_iops = init_iops_siimage, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .port_ops = p_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .dma_ops = &sil_dma_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .pio_mask = ATA_PIO4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .mwdma_mask = ATA_MWDMA2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .udma_mask = ATA_UDMA6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct ide_port_info siimage_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * siimage_init_one - PCI layer discovery entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * @id: ident table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * We then use the IDE PCI generic helper to do most of the work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) void __iomem *ioaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) resource_size_t bar5 = pci_resource_start(dev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned long barsize = pci_resource_len(dev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u8 BA5_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) d = siimage_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int first = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) printk(KERN_INFO DRV_NAME ": For full SATA support you "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "should use the libata sata_sil module.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rc = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) pci_read_config_byte(dev, 0x8A, &BA5_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if ((BA5_EN & 0x01) || bar5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Drop back to PIO if we can't map the MMIO. Some systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * seem to get terminally confused in the PCI spaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!request_mem_region(bar5, barsize, d.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "available\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ioaddr = pci_ioremap_bar(dev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ioaddr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) release_mem_region(bar5, barsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rc = ide_pci_init_one(dev, &d, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) release_mem_region(bar5, barsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static void siimage_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) void __iomem *ioaddr = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) resource_size_t bar5 = pci_resource_start(dev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned long barsize = pci_resource_len(dev, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) iounmap(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) release_mem_region(bar5, barsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct pci_device_id siimage_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static struct pci_driver siimage_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .name = "SiI_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .id_table = siimage_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .probe = siimage_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .remove = siimage_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int __init siimage_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ide_pci_register_driver(&siimage_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static void __exit siimage_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pci_unregister_driver(&siimage_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) module_init(siimage_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) module_exit(siimage_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) MODULE_AUTHOR("Andre Hedrick, Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) MODULE_DESCRIPTION("PCI driver module for SiI IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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