^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1995-1998 Mark Lord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007-2009 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ide_setup_pci_baseregs - place a PCI IDE controller native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @dev: PCI device of interface to switch native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @name: Name of interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * We attempt to place the PCI interface into PCI native mode. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * we succeed the BARs are ok and the controller is in PCI mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Returns 0 on success or an errno code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * FIXME: if we program the interface and then fail to set the BARS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * we don't switch it back to legacy mode. Do we actually care ??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int ide_setup_pci_baseregs(struct pci_dev *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 progif = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Place both IDE interfaces into PCI "native" mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (progif & 5) != 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if ((progif & 0xa) != 0xa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) printk(KERN_INFO "%s %s: device not capable of full "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "native PCI mode\n", name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) printk(KERN_INFO "%s %s: placing both ports into native PCI "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "mode\n", name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (progif & 5) != 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) printk(KERN_ERR "%s %s: rewrite of PROGIF failed, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "wanted 0x%04x, got 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) name, pci_name(dev), progif | 5, progif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int ide_pci_clear_simplex(unsigned long dma_base, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 dma_stat = inb(dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) outb(dma_stat & 0x60, dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dma_stat = inb(dma_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return (dma_stat & 0x80) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * ide_pci_dma_base - setup BMIBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @hwif: IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Fetch the DMA Bus-Master-I/O-Base-Address (BMIBA) from PCI space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long ide_pci_dma_base(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long dma_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (hwif->host_flags & IDE_HFLAG_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return hwif->dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (hwif->mate && hwif->mate->dma_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dma_base = hwif->mate->dma_base - (hwif->channel ? 0 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 baridx = (d->host_flags & IDE_HFLAG_CS5520) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dma_base = pci_resource_start(dev, baridx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (dma_base == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) printk(KERN_ERR "%s %s: DMA base is invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (hwif->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dma_base += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EXPORT_SYMBOL_GPL(ide_pci_dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ide_pci_check_simplex(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (d->host_flags & (IDE_HFLAG_MMIO | IDE_HFLAG_CS5520))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (d->host_flags & IDE_HFLAG_CLEAR_SIMPLEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ide_pci_clear_simplex(hwif->dma_base, d->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) printk(KERN_INFO "%s %s: simplex device: DMA forced\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * If the device claims "simplex" DMA, this means that only one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * the two interfaces can be trusted with DMA at any point in time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * (so we should enable DMA only on one of the two interfaces).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * FIXME: At this point we haven't probed the drives so we can't make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * the appropriate decision. Really we should defer this problem until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * we tune the drive then try to grab DMA ownership if we want to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * the DMA end. This has to be become dynamic to handle hot-plug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if ((dma_stat & 0x80) && hwif->mate && hwif->mate->dma_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) printk(KERN_INFO "%s %s: simplex device: DMA disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(ide_pci_check_simplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Set up BM-DMA capability (PnP BIOS should have done this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ide_pci_set_master(struct pci_dev *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 pcicmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if ((pcicmd & PCI_COMMAND_MASTER) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) (pcicmd & PCI_COMMAND_MASTER) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) printk(KERN_ERR "%s %s: error updating PCICMD\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXPORT_SYMBOL_GPL(ide_pci_set_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void ide_setup_pci_noise(struct pci_dev *dev, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) printk(KERN_INFO "%s %s: IDE controller (0x%04x:0x%04x rev 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) d->name, pci_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev->vendor, dev->device, dev->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EXPORT_SYMBOL_GPL(ide_setup_pci_noise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * ide_pci_enable - do PCI enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @bars: PCI BARs mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Enable the IDE PCI device. We attempt to enable the device in full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * but if that fails then we only need IO space. The PCI code should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * have setup the proper resources for us already for controllers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * legacy mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Returns zero on success or an error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int ide_pci_enable(struct pci_dev *dev, int bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pci_enable_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = pci_enable_device_io(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) printk(KERN_WARNING "%s %s: couldn't enable device\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) printk(KERN_WARNING "%s %s: BIOS configuration fixed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * assume all devices can do 32-bit DMA for now, we can add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * a DMA mask field to the struct ide_port_info if we need it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * (or let lower level driver set the DMA mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) printk(KERN_ERR "%s %s: can't set DMA mask\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = pci_request_selected_regions(dev, bars, d->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk(KERN_ERR "%s %s: can't reserve resources\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * ide_pci_configure - configure an unconfigured device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Enable and configure the PCI device we have been passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Returns zero on success or an error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int ide_pci_configure(struct pci_dev *dev, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u16 pcicmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * PnP BIOS was *supposed* to have setup this device, but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * can do it ourselves, so long as the BIOS has assigned an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * (or possibly the device is using a "legacy header" for IRQs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Maybe the user deliberately *disabled* the device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * but we'll eventually ignore it again if no drives respond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ide_setup_pci_baseregs(dev, d->name) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) printk(KERN_INFO "%s %s: device disabled (BIOS)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) printk(KERN_ERR "%s %s: error accessing PCI regs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!(pcicmd & PCI_COMMAND_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) printk(KERN_ERR "%s %s: unable to enable IDE controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * ide_pci_check_iomem - check a register is I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @bar: BAR number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Checks if a BAR is configured and points to MMIO space. If so,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * return an error code. Otherwise return 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int ide_pci_check_iomem(struct pci_dev *dev, const struct ide_port_info *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ulong flags = pci_resource_flags(dev, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Unconfigured ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!flags || pci_resource_len(dev, bar) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* I/O space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * ide_hw_configure - configure a struct ide_hw instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @dev: PCI device holding interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @port: port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @hw: struct ide_hw instance corresponding to this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Perform the initial set up for the hardware interface structure. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * is done per interface port rather than per PCI device. There may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * more than one port per device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Returns zero on success or an error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int ide_hw_configure(struct pci_dev *dev, const struct ide_port_info *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unsigned int port, struct ide_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long ctl = 0, base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if ((d->host_flags & IDE_HFLAG_ISA_PORTS) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ide_pci_check_iomem(dev, d, 2 * port) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ide_pci_check_iomem(dev, d, 2 * port + 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) printk(KERN_ERR "%s %s: I/O baseregs (BIOS) are "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "reported as MEM for port %d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) d->name, pci_name(dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ctl = pci_resource_start(dev, 2*port+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) base = pci_resource_start(dev, 2*port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Use default values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ctl = port ? 0x374 : 0x3f4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) base = port ? 0x170 : 0x1f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!base || !ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) printk(KERN_ERR "%s %s: bad PCI BARs for port %d, skipping\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) d->name, pci_name(dev), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) memset(hw, 0, sizeof(*hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hw->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ide_std_init_ports(hw, base, ctl | 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * ide_hwif_setup_dma - configure DMA interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @hwif: IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Set up the DMA base for the interface. Enable the master bits as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * necessary and attempt to bring the device DMA into a ready to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ide_hwif_setup_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if ((d->host_flags & IDE_HFLAG_NO_AUTODMA) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (dev->class & 0x80))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long base = ide_pci_dma_base(hwif, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hwif->dma_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (hwif->dma_ops == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hwif->dma_ops = &sff_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ide_pci_check_simplex(hwif, d) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ide_pci_set_master(dev, d->name) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (hwif->host_flags & IDE_HFLAG_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) hwif->name, base, base + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hwif->extra_base = base + (hwif->channel ? 8 : 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ide_allocate_dma_engine(hwif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * ide_setup_pci_controller - set up IDE PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * @bars: PCI BARs mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @noisy: verbose flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Set up the PCI and controller side of the IDE interface. This brings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * up the PCI side of the device, checks that the device is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * and enables it if need be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int ide_setup_pci_controller(struct pci_dev *dev, int bars,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const struct ide_port_info *d, int noisy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u16 pcicmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (noisy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ide_setup_pci_noise(dev, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = ide_pci_enable(dev, bars, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) printk(KERN_ERR "%s %s: error accessing PCI regs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto out_free_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = ide_pci_configure(dev, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out_free_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) printk(KERN_INFO "%s %s: device enabled (Linux)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) out_free_bars:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pci_release_selected_regions(dev, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * ide_pci_setup_ports - configure ports/devices on PCI IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @hw: struct ide_hw instances corresponding to this PCI IDE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * @hws: struct ide_hw pointers table to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Scan the interfaces attached to this device and do any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * necessary per port setup. Attach the devices and ask the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * generic DMA layer to do its work for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Normally called automaticall from do_ide_pci_setup_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * but is also used directly as a helper function by some controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * where the chipset setup is not the default PCI IDE one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) void ide_pci_setup_ports(struct pci_dev *dev, const struct ide_port_info *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct ide_hw *hw, struct ide_hw **hws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int channels = (d->host_flags & IDE_HFLAG_SINGLE) ? 1 : 2, port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * Set up the IDE ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) for (port = 0; port < channels; ++port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const struct ide_pci_enablebit *e = &d->enablebits[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) (tmp & e->mask) != e->val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) printk(KERN_INFO "%s %s: IDE port disabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) continue; /* port not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ide_hw_configure(dev, d, port, hw + port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *(hws + port) = hw + port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) EXPORT_SYMBOL_GPL(ide_pci_setup_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * ide_setup_pci_device() looks at the primary/secondary interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * on a PCI IDE device and, if they are enabled, prepares the IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * for use with them. This generic code works for most PCI chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * One thing that is not standardized is the location of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * primary/secondary interface "enable/disable" bits. For chipsets that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * we "know" about, this information is in the struct ide_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * for all other chipsets, we just assume both interfaces are enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int do_ide_setup_pci_device(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const struct ide_port_info *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 noisy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int pciirq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Can we trust the reported IRQ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pciirq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * This allows offboard ide-pci cards the enable a BIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * verify interrupt settings of split-mirror pci-config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * space, place chipset into init-mode, and/or preserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * an interrupt if the card is not native ide support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = d->init_chipset ? d->init_chipset(dev) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ide_pci_is_in_compatibility_mode(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (noisy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk(KERN_INFO "%s %s: not 100%% native mode: will "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "probe irqs later\n", d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pciirq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else if (!pciirq && noisy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) printk(KERN_WARNING "%s %s: bad irq (%d): will probe later\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) d->name, pci_name(dev), pciirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else if (noisy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) printk(KERN_INFO "%s %s: 100%% native mode on irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) d->name, pci_name(dev), pciirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = pciirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ide_pci_init_two(struct pci_dev *dev1, struct pci_dev *dev2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const struct ide_port_info *d, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct pci_dev *pdev[] = { dev1, dev2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ide_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int ret, i, n_ports = dev2 ? 4 : 2, bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct ide_hw hw[4], *hws[] = { NULL, NULL, NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (d->host_flags & IDE_HFLAG_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bars = (1 << 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bars = (1 << 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if ((d->host_flags & IDE_HFLAG_NO_DMA) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (d->host_flags & IDE_HFLAG_CS5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bars |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bars |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < n_ports / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = ide_setup_pci_controller(pdev[i], bars, d, !i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (i == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pci_release_selected_regions(pdev[0], bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ide_pci_setup_ports(pdev[i], d, &hw[i*2], &hws[i*2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) host = ide_host_alloc(d, hws, n_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto out_free_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) host->dev[0] = &dev1->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) host->dev[1] = &dev2->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) host->host_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) host->irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pci_set_drvdata(pdev[0], host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pci_set_drvdata(pdev[1], host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for (i = 0; i < n_ports / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = do_ide_setup_pci_device(pdev[i], d, !i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * FIXME: Mom, mom, they stole me the helper function to undo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * do_ide_setup_pci_device() on the first device!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) goto out_free_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* fixup IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ide_pci_is_in_compatibility_mode(pdev[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) hw[i*2].irq = pci_get_legacy_ide_irq(pdev[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hw[i*2 + 1].irq = pci_get_legacy_ide_irq(pdev[i], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) hw[i*2 + 1].irq = hw[i*2].irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = ide_host_register(host, d, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ide_host_free(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) out_free_bars:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) i = n_ports / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pci_release_selected_regions(pdev[i], bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) EXPORT_SYMBOL_GPL(ide_pci_init_two);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int ide_pci_init_one(struct pci_dev *dev, const struct ide_port_info *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return ide_pci_init_two(dev, NULL, d, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) EXPORT_SYMBOL_GPL(ide_pci_init_one);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) void ide_pci_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (host->host_flags & IDE_HFLAG_SINGLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) bars = (1 << 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bars = (1 << 4) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if ((host->host_flags & IDE_HFLAG_NO_DMA) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (host->host_flags & IDE_HFLAG_CS5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) bars |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) bars |= (1 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ide_host_remove(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pci_release_selected_regions(dev2, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pci_release_selected_regions(dev, bars);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pci_disable_device(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) EXPORT_SYMBOL_GPL(ide_pci_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ide_pci_suspend(struct pci_dev *dev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) pci_save_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pci_set_power_state(dev, pci_choose_state(dev, state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) EXPORT_SYMBOL_GPL(ide_pci_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) int ide_pci_resume(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pci_set_power_state(dev, PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rc = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pci_restore_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pci_set_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (host->init_chipset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) host->init_chipset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) EXPORT_SYMBOL_GPL(ide_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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