Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 1998-2000 Michel Aubry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Portions copyright (c) 2001 Sun Microsystems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * RCC/ServerWorks IDE driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *         supports UDMA mode 2 (33 MB/s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *         all revisions support UDMA mode 4 (66 MB/s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *         *** The CSB5 does not provide ANY register ***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *         *** to detect 80-conductor cable presence. ***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *   controller same as the CSB6. Single channel ATA100 only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	Available under NDA only. Errata info very hard to get.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DRV_NAME "serverworks"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SVWKS_CSB5_REVISION_NEW	0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SVWKS_CSB6_REVISION	0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * can overrun their FIFOs when used with the CSB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const char *svwks_bad_ata100[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	"ST320011A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	"ST340016A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	"ST360021A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	"ST380021A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int check_in_drive_lists (ide_drive_t *drive, const char **list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	char *m = (char *)&drive->id[ATA_ID_PROD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	while (*list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		if (!strcmp(*list++, m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static u8 svwks_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		return 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	} else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		return 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		u8 btr = 0, mode, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		pci_read_config_byte(dev, 0x5A, &btr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		mode = btr & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		/* If someone decides to do UDMA133 on CSB5 the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		   issue will bite so be inclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			mode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		switch(mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		case 3:	 mask = 0x3f; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		case 2:	 mask = 0x1f; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		case 1:	 mask = 0x07; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		default: mask = 0x00; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static u8 svwks_csb_check (struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void svwks_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (drive->dn >= ARRAY_SIZE(drive_pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (svwks_csb_check(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		u16 csb_pio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		pci_read_config_word(dev, 0x4a, &csb_pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		csb_pio &= ~(0x0f << (4 * drive->dn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		csb_pio |= (pio << (4 * drive->dn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		pci_write_config_word(dev, 0x4a, csb_pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void svwks_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	static const u8 udma_modes[]		= { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	static const u8 dma_modes[]		= { 0x77, 0x21, 0x20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	static const u8 drive_pci2[]		= { 0x45, 0x44, 0x47, 0x46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	const u8 speed		= drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u8 unit			= drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	u8 ultra_enable	 = 0, ultra_timing = 0, dma_timing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (drive->dn >= ARRAY_SIZE(drive_pci2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	pci_read_config_byte(dev, 0x54, &ultra_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ultra_timing	&= ~(0x0F << (4*unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ultra_enable	&= ~(0x01 << drive->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		dma_timing   |= dma_modes[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ultra_enable |= (0x01 << drive->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	} else if (speed >= XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dma_timing   |= dma_modes[speed - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	pci_write_config_byte(dev, 0x54, ultra_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int init_chipset_svwks(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u8 btr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* force Master Latency Timer value to 64 PCICLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* OSB4 : South Bridge and IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		struct pci_dev *isa_dev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		if (isa_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			pci_read_config_dword(isa_dev, 0x64, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			reg &= ~0x00002000; /* disable 600ns interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			if(!(reg & 0x00004000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					"enabled.\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			reg |=  0x00004000; /* enable UDMA/33 support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			pci_write_config_dword(isa_dev, 0x64, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			pci_dev_put(isa_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* setup CSB5/CSB6 : South Bridge and IDE option RAID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/* Third Channel Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (!(PCI_FUNC(dev->devfn) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			struct pci_dev * findev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			u32 reg4c = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 				PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			if (findev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				pci_read_config_dword(findev, 0x4C, &reg4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				reg4c &= ~0x000007FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				reg4c |=  0x00000040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				reg4c |=  0x00000020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				pci_write_config_dword(findev, 0x4C, reg4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				pci_dev_put(findev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			outb_p(0x06, 0x0c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			dev->irq = inb_p(0x0c01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			struct pci_dev * findev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			u8 reg41 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 					PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			if (findev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				pci_read_config_byte(findev, 0x41, &reg41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				reg41 &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				pci_write_config_byte(findev, 0x41, reg41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				pci_dev_put(findev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			 * This is a device pin issue on CSB6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			 * Since there will be a future raid mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			 * early versions of the chipset require the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			 * interrupt pin to be set, and it is a compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 			 * mode issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) //		pci_read_config_dword(dev, 0x40, &pioreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) //		pci_write_config_dword(dev, 0x40, 0x99999999);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) //		pci_read_config_dword(dev, 0x44, &dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) //		pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		/* setup the UDMA Control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		 * 1. clear bit 6 to enable DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		 * 2. enable DMA modes with bits 0-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		 * 	00 : legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		 * 	01 : udma2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		 * 	10 : udma2/udma4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		 * 	11 : udma2/udma4/udma5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		pci_read_config_byte(dev, 0x5A, &btr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		btr &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (!(PCI_FUNC(dev->devfn) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			btr |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		pci_write_config_byte(dev, 0x5A, btr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	/* Setup HT1000 SouthBridge Controller - Single Channel Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pci_read_config_byte(dev, 0x5A, &btr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		btr &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		btr |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		pci_write_config_byte(dev, 0x5A, btr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * of the subsystem device ID indicate presence of an 80-pin cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * Bit 15 set   = secondary IDE channel has 80-pin cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * Bit 14 set   = primary IDE channel has 80-pin cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static u8 ata66_svwks_dell(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	     dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return ((1 << (hwif->channel + 14)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Sun Cobalt Alpine hardware avoids the 80-pin cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  * detect issue by attaching the drives directly to the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  * This check follows the Dell precedent (how scary is that?!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * WARNING: this only works on Alpine hardware!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	    dev->vendor	== PCI_VENDOR_ID_SERVERWORKS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	    dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return ((1 << (hwif->channel + 14)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static u8 svwks_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	/* Server Works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ata66_svwks_svwks (hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* Dell PowerEdge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return ata66_svwks_dell (hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* Cobalt Alpine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return ata66_svwks_cobalt (hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* Per Specified Design by OEM, and ASIC Architect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	    (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct ide_port_ops osb4_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.set_pio_mode		= svwks_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.set_dma_mode		= svwks_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct ide_port_ops svwks_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.set_pio_mode		= svwks_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.set_dma_mode		= svwks_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.udma_filter		= svwks_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.cable_detect		= svwks_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct ide_port_info serverworks_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	{	/* 0: OSB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.init_chipset	= init_chipset_svwks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.port_ops	= &osb4_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.udma_mask	= 0x00, /* UDMA is problematic on OSB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	{	/* 1: CSB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.init_chipset	= init_chipset_svwks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.port_ops	= &svwks_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	{	/* 2: CSB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.init_chipset	= init_chipset_svwks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.port_ops	= &svwks_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	{	/* 3: CSB6-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.init_chipset	= init_chipset_svwks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.port_ops	= &svwks_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.host_flags	= IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{	/* 4: HT1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		.init_chipset	= init_chipset_svwks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		.port_ops	= &svwks_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		.host_flags	= IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)  *	svwks_init_one	-	called when a OSB/CSB is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)  *	@dev: the svwks device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  *	@id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)  *	Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  *	finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	d = serverworks_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (idx == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	else if (idx == 2 || idx == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		if ((PCI_FUNC(dev->devfn) & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			if (pci_resource_start(dev, 0) != 0x01f1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 				d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			d.host_flags |= IDE_HFLAG_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			d.host_flags &= ~IDE_HFLAG_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct pci_device_id svwks_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE),   0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE),   1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE),   2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2),  3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{ PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct pci_driver svwks_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.name		= "Serverworks_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.id_table	= svwks_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.probe		= svwks_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int __init svwks_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return ide_pci_register_driver(&svwks_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void __exit svwks_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	pci_unregister_driver(&svwks_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) module_init(svwks_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) module_exit(svwks_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_LICENSE("GPL");