Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2003 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Publicly available from Intel web site. Errata documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * is also publicly available. As an aide to anyone hacking on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * driver the list of errata that are relevant is below.going back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * PIIX4. Older device documentation is now a bit tricky to find.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Errata of note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Unfixable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	PIIX4    errata #9	- Only on ultra obscure hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *	ICH3	 errata #13     - Not observed to affect real hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *				  by Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Things we must deal with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	PIIX4	errata #10	- BM IDE hang with non UDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *				  (must stop/start dma to recover)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	440MX   errata #15	- As PIIX4 errata #10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	PIIX4	errata #15	- Must not read control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * 				  during a PIO transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *	440MX   errata #13	- As PIIX4 errata #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	ICH2	errata #21	- DMA mode 0 doesn't work right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *	ICH0/1  errata #55	- As ICH2 errata #21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *	ICH2	spec c #9	- Extra operations needed to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *				  drive hotswap [NOT YET SUPPORTED]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *	ICH2    spec c #20	- IDE PRD must not cross a 64K boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *				  and must be dword aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *	ICH2    spec c #24	- UDMA mode 4,5 t85/86 should be 6ns not 3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * Should have been BIOS fixed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	450NX:	errata #19	- DMA hangs on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	450NX:  errata #20	- DMA hangs on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *	450NX:  errata #25	- Corruption with DMA on old 450NX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *	ICH3    errata #15      - IDE deadlock under high load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *				  (BIOS must set dev 31 fn 0 bit 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *	ICH3	errata #18	- Don't use native mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DRV_NAME "piix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int no_piix_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	piix_set_pio_mode	-	set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *	@port: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *	Set the interface PIO mode based upon the settings done by AMI BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void piix_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int is_slave		= drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int master_port		= hwif->channel ? 0x42 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int slave_port		= 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u16 master_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 slave_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	static DEFINE_SPINLOCK(tune_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				     /* ISP  RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	static const u8 timings[][2]= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					{ 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					{ 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					{ 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 					{ 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 * Master vs slave is synchronized above us but the slave register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * shared by the two hwifs so the corner case of two slave timeouts in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * parallel must be locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spin_lock_irqsave(&tune_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	pci_read_config_word(dev, master_port, &master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		control |= 1;	/* Programmable timing on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (drive->media == ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		control |= 4;	/* Prefetch, post write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (ide_pio_need_iordy(drive, pio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		control |= 2;	/* IORDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		master_data |=  0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		master_data &= ~0x0070;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (pio > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			/* Set PPE, IE and TIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			master_data |= control << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		pci_read_config_byte(dev, slave_port, &slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		slave_data &= hwif->channel ? 0x0f : 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			       (hwif->channel ? 4 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		master_data &= ~0x3307;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (pio > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			/* enable PPE, IE and TIME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			master_data |= control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pci_write_config_word(dev, master_port, master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	if (is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		pci_write_config_byte(dev, slave_port, slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	spin_unlock_irqrestore(&tune_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *	piix_set_dma_mode	-	set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *	@hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  *	Set a PIIX host controller to the desired DMA mode.  This involves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  *	programming the right timing data into the PCI configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void piix_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8 maslave		= hwif->channel ? 0x42 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int a_speed		= 3 << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int u_flag		= 1 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int v_flag		= 0x01 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int w_flag		= 0x10 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	int u_speed		= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	int			sitre;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u16			reg4042, reg4a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u8			reg48, reg54, reg55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	const u8 speed		= drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	pci_read_config_word(dev, maslave, &reg4042);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	sitre = (reg4042 & 0x4000) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	pci_read_config_byte(dev, 0x48, &reg48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	pci_read_config_word(dev, 0x4a, &reg4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	pci_read_config_byte(dev, 0x54, &reg54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pci_read_config_byte(dev, 0x55, &reg55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		u8 udma = speed - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (!(reg48 & u_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			pci_write_config_byte(dev, 0x48, reg48 | u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		if (speed == XFER_UDMA_5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if ((reg4a & a_speed) != u_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (speed > XFER_UDMA_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			if (!(reg54 & v_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				pci_write_config_byte(dev, 0x54, reg54 | v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		const u8 mwdma_to_pio[] = { 0, 3, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		if (reg48 & u_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		if (reg4a & a_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (reg54 & v_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (reg55 & w_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (speed >= XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			drive->pio_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		piix_set_pio_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *	init_chipset_ich	-	set up the ICH chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *	@dev: PCI device to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  *	Initialize the PCI device as required.  For the ICH this turns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *	out to be nice and simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int init_chipset_ich(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 extra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	pci_read_config_dword(dev, 0x54, &extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	pci_write_config_dword(dev, 0x54, extra | 0x400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  *	ich_clear_irq	-	clear BMDMA status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *	@drive: IDE drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *	ICHx contollers set DMA INTR no matter DMA or PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  *	BMDMA status might need to be cleared even for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *	PIO interrupts to prevent spurious/lost IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void ich_clear_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u8 dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * ide_dma_end() needs BMDMA status for error checking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * So, skip clearing BMDMA status here and leave it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * to ide_dma_end() if this is DMA interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (drive->waiting_for_dma || hwif->dma_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	/* clear the INTR & ERROR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* Should we force the bit as well ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ich_laptop {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u16 subvendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	u16 subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *	List of laptops that use short cables rather than 80 wire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct ich_laptop ich_laptop[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* devid, subvendor, subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	{ 0x27DF, 0x1025, 0x0102 },	/* ICH7 on Acer 5602aWLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ 0x27DF, 0x0005, 0x0280 },	/* ICH7 on Acer 5602WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{ 0x27DF, 0x1025, 0x0110 },	/* ICH7 on Acer 3682WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	{ 0x27DF, 0x1043, 0x1267 },	/* ICH7 on Asus W5F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	{ 0x27DF, 0x103C, 0x30A1 },	/* ICH7 on HP Compaq nc2400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{ 0x27DF, 0x1071, 0xD221 },	/* ICH7 on Hercules EC-900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{ 0x24CA, 0x1025, 0x0061 },	/* ICH4 on Acer Aspire 2023WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	{ 0x24CA, 0x1025, 0x003d },	/* ICH4 on ACER TM290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	{ 0x266F, 0x1025, 0x0066 },	/* ICH6 on ACER Aspire 1694WLMi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	{ 0x2653, 0x1043, 0x82D8 },	/* ICH6M on Asus Eee 701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ 0x27df, 0x104d, 0x900e },	/* ICH7 on Sony TZ-90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static u8 piix_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	const struct ich_laptop *lap = &ich_laptop[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* check for specials */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	while (lap->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		if (lap->device == pdev->device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		    lap->subvendor == pdev->subsystem_vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		    lap->subdevice == pdev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			return ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		lap++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	pci_read_config_byte(pdev, 0x54, &reg54h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  *	init_hwif_piix		-	fill in the hwif for the PIIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  *	@hwif: IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  *	Set up the ide_hwif_t for the PIIX interface according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  *	capabilities of the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void init_hwif_piix(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!hwif->dma_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (no_piix_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct ide_port_ops piix_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.set_pio_mode		= piix_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.set_dma_mode		= piix_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.cable_detect		= piix_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct ide_port_ops ich_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.set_pio_mode		= piix_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.set_dma_mode		= piix_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.clear_irq		= ich_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.cable_detect		= piix_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define DECLARE_PIIX_DEV(udma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.name		= DRV_NAME,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.init_hwif	= init_hwif_piix,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.port_ops	= &piix_port_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		.pio_mask	= ATA_PIO4,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		.swdma_mask	= ATA_SWDMA2_ONLY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		.mwdma_mask	= ATA_MWDMA12_ONLY,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		.udma_mask	= udma,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DECLARE_ICH_DEV(mwdma, udma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.name		= DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.init_chipset	= init_chipset_ich, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.init_hwif	= init_hwif_piix, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.enablebits	= {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.port_ops	= &ich_port_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.pio_mask	= ATA_PIO4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.swdma_mask	= ATA_SWDMA2_ONLY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.mwdma_mask	= mwdma, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.udma_mask	= udma, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct ide_port_info piix_pci_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* 0: MPIIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		 * MPIIX actually has only a single IDE channel mapped to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		 * the primary or secondary ports depending on the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		 * of the bit 14 of the IDETIM register at offset 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.enablebits	= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.host_flags	= IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		/* This is a painful system best to let it self tune for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	/* 1: PIIXa/PIIXb/PIIX3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	DECLARE_PIIX_DEV(0x00), /* no udma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	/* 2: PIIX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	DECLARE_PIIX_DEV(ATA_UDMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	/* 3: ICH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	/* 4: ICH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	/* 5: PIIX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	DECLARE_PIIX_DEV(ATA_UDMA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* 6: ICH[2-6]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	DECLARE_ICH_DEV(ATA_MWDMA12_ONLY, ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* 7: ICH7/7-R, no MWDMA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	DECLARE_ICH_DEV(ATA_MWDMA2_ONLY, ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  *	piix_init_one	-	called when a PIIX is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  *	@dev: the piix device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)  *	@id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)  *	Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)  *	finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)  *	piix_check_450nx	-	Check for problem 450NX setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)  *	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)  *	Check for the present of 450NX errata #19 and errata #25. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)  *	they are found, disable use of DMA IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static void piix_check_450nx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	u16 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		/* Look for 450NX PXB. Check for problem configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		   A PCI quirk checks bit 6 already */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		pci_read_config_word(pdev, 0x41, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		/* Only on the original revision: IDE DMA can hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (pdev->revision == 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			no_piix_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		/* On all revisions below 5 PXB bus lock must be disabled for IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		else if (cfg & (1<<14) && pdev->revision < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			no_piix_dma = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if(no_piix_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if(no_piix_dma == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct pci_device_id piix_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),  1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),  1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),    0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),  1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),    2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),  3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),  2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),  4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),  5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),    2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static struct pci_driver piix_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.name		= "PIIX_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.id_table	= piix_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.probe		= piix_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int __init piix_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	piix_check_450nx();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	return ide_pci_register_driver(&piix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void __exit piix_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	pci_unregister_driver(&piix_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) module_init(piix_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_exit(piix_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_LICENSE("GPL");