^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006-2007, 2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Portions Copyright (C) 1999 Promise Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Frank Tiernan (frankt@promise.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Released under terms of General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRV_NAME "pdc202xx_old"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void pdc202xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 drive_pci = 0x60 + (drive->dn << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 AP = 0, BP = 0, CP = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 TA = 0, TB = 0, TC = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pci_read_config_byte(dev, drive_pci, &AP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) pci_read_config_byte(dev, drive_pci + 1, &BP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) pci_read_config_byte(dev, drive_pci + 2, &CP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) switch(speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) case XFER_UDMA_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) case XFER_UDMA_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case XFER_UDMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case XFER_PIO_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) default: TA = 0x09; TB = 0x13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (speed < XFER_SW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * preserve SYNC_INT / ERDDY_EN bits while clearing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) AP &= ~0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ide_pio_need_iordy(drive, speed - XFER_PIO_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) AP |= 0x20; /* set IORDY_EN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (drive->media == ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) AP |= 0x10; /* set Prefetch_EN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* clear PB[4:0] bits of register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BP &= ~0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pci_write_config_byte(dev, drive_pci, AP | TA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pci_write_config_byte(dev, drive_pci + 1, BP | TB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* clear MB[2:0] bits of register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) BP &= ~0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* clear MC[3:0] bits of register C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CP &= ~0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pci_write_config_byte(dev, drive_pci + 1, BP | TB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_write_config_byte(dev, drive_pci + 2, CP | TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void pdc202xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) drive->dma_mode = drive->pio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pdc202xx_set_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int pdc202xx_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long high_16 = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 sc1d = inb(high_16 + 0x1d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (hwif->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * bit 7: error, bit 6: interrupting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * bit 5: FIFO full, bit 4: FIFO empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return (sc1d & 0x40) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * bit 3: error, bit 2: interrupting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * bit 1: FIFO full, bit 0: FIFO empty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return (sc1d & 0x04) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pci_read_config_word(dev, 0x50, &CIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Set the control register to use the 66MHz system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * clock for UDMA 3/4/5 mode operation when necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * FIXME: this register is shared by both channels, some locking is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * It may also be possible to leave the 66MHz clock on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * and readjust the timing parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long clock_reg = hwif->extra_base + 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u8 clock = inb(clock_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long clock_reg = hwif->extra_base + 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 clock = inb(clock_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void pdc2026x_init_hwif(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pdc_old_disable_66MHz_clock(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void pdc202xx_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (drive->current_speed > XFER_UDMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pdc_old_enable_66MHz_clock(drive->hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct request *rq = hwif->rq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long high_16 = hwif->extra_base - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 word_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 clock = inb(high_16 + 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) word_count = (blk_rq_sectors(rq) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) word_count = (rq_data_dir(rq) == READ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) word_count | 0x05000000 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) word_count | 0x06000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) outl(word_count, atapi_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int pdc202xx_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long high_16 = hwif->extra_base - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 clock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) outl(0, atapi_reg); /* zero out extra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clock = inb(high_16 + 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (drive->current_speed > XFER_UDMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pdc_old_disable_66MHz_clock(drive->hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int init_chipset_pdc202xx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long dmabase = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (dmabase == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) udma_speed_flag = inb(dmabase | 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) primary_mode = inb(dmabase | 0x1a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) secondary_mode = inb(dmabase | 0x1b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "Primary %s Mode " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "Secondary %s Mode.\n", pci_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (udma_speed_flag & 1) ? "EN" : "DIS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (primary_mode & 1) ? "MASTER" : "PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (secondary_mode & 1) ? "MASTER" : "PCI" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!(udma_speed_flag & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pci_name(dev), udma_speed_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (udma_speed_flag|1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb(udma_speed_flag | 1, dmabase | 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void pdc202ata4_fixup_irq(struct pci_dev *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 irq = 0, irq2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (irq != irq2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_write_config_byte(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk(KERN_INFO "%s %s: PCI config space interrupt "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "mirror fixed\n", name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IDE_HFLAGS_PDC202XX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (IDE_HFLAG_ERROR_STOPS_FIFO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IDE_HFLAG_OFF_BOARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct ide_port_ops pdc20246_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .set_pio_mode = pdc202xx_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .set_dma_mode = pdc202xx_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .test_irq = pdc202xx_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct ide_port_ops pdc2026x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .set_pio_mode = pdc202xx_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .set_dma_mode = pdc202xx_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .test_irq = pdc202xx_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .cable_detect = pdc2026x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct ide_dma_ops pdc2026x_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .dma_start = pdc202xx_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dma_end = pdc202xx_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .dma_test_irq = ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DECLARE_PDC2026X_DEV(udma, sectors) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .init_chipset = init_chipset_pdc202xx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .init_hwif = pdc2026x_init_hwif, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .port_ops = &pdc2026x_port_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .dma_ops = &pdc2026x_dma_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .host_flags = IDE_HFLAGS_PDC202XX, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .pio_mask = ATA_PIO4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .mwdma_mask = ATA_MWDMA2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .udma_mask = udma, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .max_sectors = sectors, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct ide_port_info pdc202xx_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { /* 0: PDC20246 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .init_chipset = init_chipset_pdc202xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .port_ops = &pdc20246_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .dma_ops = &sff_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .host_flags = IDE_HFLAGS_PDC202XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* 1: PDC2026{2,3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* 2: PDC2026{5,7}: UDMA5, limit LBA48 requests to 256 sectors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_PDC2026X_DEV(ATA_UDMA5, 256),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * pdc202xx_init_one - called when a PDC202xx is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @dev: the pdc202xx device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int pdc202xx_init_one(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) const struct ide_port_info *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) d = &pdc202xx_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (idx < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pdc202ata4_fixup_irq(dev, d->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct pci_dev *bridge = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (bridge &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bridge->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) printk(KERN_INFO DRV_NAME " %s: skipping Promise "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "PDC20265 attached to I2O RAID controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ide_pci_init_one(dev, d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct pci_device_id pdc202xx_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static struct pci_driver pdc202xx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "Promise_Old_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .id_table = pdc202xx_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .probe = pdc202xx_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int __init pdc202xx_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ide_pci_register_driver(&pdc202xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void __exit pdc202xx_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) pci_unregister_driver(&pdc202xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) module_init(pdc202xx_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) module_exit(pdc202xx_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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