^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Promise TX2/TX4/TX2000/133 IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Split from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005-2007 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Portions Copyright (C) 1999 Promise Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Frank Tiernan (frankt@promise.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Released under terms of General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRV_NAME "pdc202xx_new"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DBG(fmt, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static u8 max_dma_rate(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) switch(pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) case PCI_DEVICE_ID_PROMISE_20277:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) case PCI_DEVICE_ID_PROMISE_20276:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case PCI_DEVICE_ID_PROMISE_20275:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) case PCI_DEVICE_ID_PROMISE_20271:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case PCI_DEVICE_ID_PROMISE_20269:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mode = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) case PCI_DEVICE_ID_PROMISE_20270:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case PCI_DEVICE_ID_PROMISE_20268:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mode = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * get_indexed_reg - Get indexed register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @hwif: for the port address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @index: index of the indexed register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) outb(index, hwif->dma_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) value = inb(hwif->dma_base + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DBG("index[%02X] value[%02X]\n", index, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * set_indexed_reg - Set indexed register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @hwif: for the port address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @index: index of the indexed register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) outb(index, hwif->dma_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) outb(value, hwif->dma_base + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DBG("index[%02X] value[%02X]\n", index, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * ATA Timing Tables based on 133 MHz PLL output clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * If the PLL outputs 100 MHz clock, the ASIC hardware will set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * the timing registers automatically when "set features" command is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * issued to the device. However, if the PLL output clock is 133 MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * the following tables must be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct pio_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 reg0c, reg0d, reg13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } pio_timings [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct mwdma_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 reg0e, reg0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } mwdma_timings [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 0xdf, 0x5f }, /* MWDMA mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 0x6b, 0x27 }, /* MWDMA mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { 0x69, 0x25 }, /* MWDMA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct udma_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 reg10, reg11, reg12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } udma_timings [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void pdcnew_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * IDE core issues SETFEATURES_XFER to the drive first (thanks to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * automatically set the timing registers based on 100 MHz PLL output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * chips, we must override the default register settings...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (max_dma_rate(dev) == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 mode = speed & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) set_indexed_reg(hwif, 0x10 + adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) udma_timings[mode].reg10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) set_indexed_reg(hwif, 0x11 + adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) udma_timings[mode].reg11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) set_indexed_reg(hwif, 0x12 + adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) udma_timings[mode].reg12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) set_indexed_reg(hwif, 0x0e + adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mwdma_timings[mode].reg0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) set_indexed_reg(hwif, 0x0f + adj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mwdma_timings[mode].reg0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else if (speed == XFER_UDMA_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Set tHOLD bit to 0 if using UDMA mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void pdcnew_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (max_dma_rate(dev) == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (get_indexed_reg(hwif, 0x0b) & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static void pdcnew_reset(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Deleted this because it is redundant from the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) drive->hwif->channel ? "Secondary" : "Primary");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * read_counter - Read the byte count registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @dma_base: for the port address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static long read_counter(u32 dma_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 cnt0, cnt1, cnt2, cnt3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) long count = 0, last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int retry = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) last = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Read the current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) outb(0x20, pri_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) cnt0 = inb(pri_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outb(0x21, pri_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) cnt1 = inb(pri_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) outb(0x20, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cnt2 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) outb(0x21, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cnt3 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * The 30-bit decrementing counter is read in 4 pieces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Incorrect value may be read when the most significant bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * are changing...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) cnt0, cnt1, cnt2, cnt3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * detect_pll_input_clock - Detect the PLL input clock in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @dma_base: for the port address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static long detect_pll_input_clock(unsigned long dma_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ktime_t start_time, end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) long start_count, end_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) long pll_input, usec_elapsed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u8 scr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) start_count = read_counter(dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) start_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Start the test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) outb(0x01, dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) scr1 = inb(dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DBG("scr1[%02X]\n", scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) outb(scr1 | 0x40, dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Let the counter run for 10 ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) end_count = read_counter(dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) end_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Stop the test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) outb(0x01, dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) scr1 = inb(dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DBG("scr1[%02X]\n", scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) outb(scr1 & ~0x40, dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Calculate the input clock in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * (the clock counter is 30 bit wide and counts down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) usec_elapsed = ktime_us_delta(end_time, start_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) (10000000 / usec_elapsed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DBG("start[%ld] end[%ld]\n", start_count, end_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return pll_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void apple_kiwi_init(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct device_node *np = pci_device_to_OF_node(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (pdev->revision >= 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Setup chip magic config stuff (from darwin) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pci_read_config_byte (pdev, 0x40, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pci_write_config_byte(pdev, 0x40, (conf | 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif /* CONFIG_PPC_PMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int init_chipset_pdcnew(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) const char *name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned long dma_base = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long sec_dma_base = dma_base + 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) long pll_input, pll_output, ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int f, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u8 pll_ctl0, pll_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (dma_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_PPC_PMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) apple_kiwi_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Calculate the required PLL output frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) switch(max_dma_rate(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 4: /* it's 133 MHz for Ultra133 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pll_output = 133333333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 3: /* and 100 MHz for Ultra100 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pll_output = 100000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Detect PLL input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * On some systems, where PCI bus is running at non-standard clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * PDC20268 and newer chips employ PLL circuit to help correct timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * registers setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pll_input = detect_pll_input_clock(dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) name, pci_name(dev), pll_input / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "\n", name, pci_name(dev), pll_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DBG("pll_output is %ld Hz\n", pll_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Show the current clock value of PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * (maybe already configured by the BIOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) outb(0x02, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pll_ctl0 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) outb(0x03, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pll_ctl1 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Calculate the ratio of F, R and NO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * POUT = (F + 2) / (( R + 2) * NO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ratio = pll_output / (pll_input / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ratio < 8600L) { /* 8.6x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Using NO = 0x01, R = 0x0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) r = 0x0d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) } else if (ratio < 12900L) { /* 12.9x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Using NO = 0x01, R = 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) r = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else if (ratio < 16100L) { /* 16.1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Using NO = 0x01, R = 0x06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) r = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else if (ratio < 64000L) { /* 64x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) r = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Invalid ratio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) name, pci_name(dev), ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) f = (ratio * (r + 2)) / 1000 - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (unlikely(f < 0 || f > 127)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Invalid F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) printk(KERN_ERR "%s %s: F[%d] invalid!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) name, pci_name(dev), f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pll_ctl0 = (u8) f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pll_ctl1 = (u8) r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) outb(0x02, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) outb(pll_ctl0, sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) outb(0x03, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) outb(pll_ctl1, sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Wait the PLL circuit to be stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mdelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Show the current clock value of PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) outb(0x02, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pll_ctl0 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) outb(0x03, sec_dma_base + 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pll_ctl1 = inb(sec_dma_base + 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static struct pci_dev *pdc20270_get_dev2(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct pci_dev *dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PCI_FUNC(dev->devfn)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (dev2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev2->vendor == dev->vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev2->device == dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (dev2->irq != dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev2->irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) printk(KERN_INFO DRV_NAME " %s: PCI config space "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "interrupt fixed\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct ide_port_ops pdcnew_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .set_pio_mode = pdcnew_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .set_dma_mode = pdcnew_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .resetproc = pdcnew_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .cable_detect = pdcnew_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define DECLARE_PDCNEW_DEV(udma) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .name = DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .init_chipset = init_chipset_pdcnew, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .port_ops = &pdcnew_port_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .host_flags = IDE_HFLAG_POST_SET_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) IDE_HFLAG_ERROR_STOPS_FIFO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) IDE_HFLAG_OFF_BOARD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .pio_mask = ATA_PIO4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .mwdma_mask = ATA_MWDMA2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .udma_mask = udma, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct ide_port_info pdcnew_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * pdc202new_init_one - called when a pdc202xx is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @dev: the pdc202new device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * @id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct pci_dev *bridge = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bridge->vendor == PCI_VENDOR_ID_DEC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bridge->device == PCI_DEVICE_ID_DEC_21150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct pci_dev *dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (PCI_SLOT(dev->devfn) & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev2 = pdc20270_get_dev2(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (dev2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret = ide_pci_init_two(dev, dev2, d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bridge->vendor == PCI_VENDOR_ID_INTEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) " skipping\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ide_pci_init_one(dev, d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void pdc202new_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct pci_device_id pdc202new_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct pci_driver pdc202new_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "Promise_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id_table = pdc202new_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .probe = pdc202new_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .remove = pdc202new_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int __init pdc202new_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ide_pci_register_driver(&pdc202new_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void __exit pdc202new_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pci_unregister_driver(&pdc202new_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) module_init(pdc202new_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) module_exit(pdc202new_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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