^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Jaromir Koutek <miri@punknet.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Jan Harkes <jaharkes@cwi.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Mark Lord <mlord@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Some parts of code are from ali14xx.c and from rz1000.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRV_NAME "opti621"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define READ_REG 0 /* index of Read cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WRITE_REG 1 /* index of Write cycle timing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CNTRL_REG 3 /* index of Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STRAP_REG 5 /* index of Strap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MISC_REG 6 /* index of Miscellaneous register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static DEFINE_SPINLOCK(opti621_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Write value to register reg, base of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * is at reg_base (0x1f0 primary, 0x170 secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * if not changed by PCI configuration).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * This is from setupvic.exe program.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void write_reg(u8 value, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) inw(reg_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) inw(reg_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) outb(3, reg_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) outb(value, reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) outb(0x83, reg_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Read value from register reg, base of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * is at reg_base (0x1f0 primary, 0x170 secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * if not changed by PCI configuration).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * This is from setupvic.exe program.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u8 read_reg(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) inw(reg_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) inw(reg_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) outb(3, reg_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = inb(reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) outb(0x83, reg_base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned long mode = drive->pio_mode, pair_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const u8 pio = mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 tim, misc, addr_pio = pio, clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* DRDY is default 2 (by OPTi Databook) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const u8 addr_timings[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const u8 data_rec_timings[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ide_set_drivedata(drive, (void *)mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pair_mode = (unsigned long)ide_get_drivedata(pair);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (pair_mode && pair_mode < mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) addr_pio = pair_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_lock_irqsave(&opti621_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg_base = hwif->io_ports.data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* allow Register-B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) outb(0xc0, reg_base + CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* hmm, setupvic.exe does this ;-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) outb(0xff, reg_base + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* if reads 0xff, adapter not exist? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (void)inb(reg_base + CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* if reads 0xc0, no interface exist? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) read_reg(CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* check CLK speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk = read_reg(STRAP_REG) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tim = data_rec_timings[clk][pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) misc = addr_timings[clk][addr_pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* select Index-0/1 for Register-A/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) write_reg(drive->dn & 1, MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* set read cycle timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) write_reg(tim, READ_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* set write cycle timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) write_reg(tim, WRITE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* use Register-A for drive 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* use Register-B for drive 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) write_reg(0x85, CNTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* set address setup, DRDY timings, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* and read prefetch for both drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) write_reg(misc, MISC_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&opti621_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct ide_port_ops opti621_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .set_pio_mode = opti621_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct ide_port_info opti621_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .port_ops = &opti621_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .host_flags = IDE_HFLAG_NO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ide_pci_init_one(dev, &opti621_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct pci_device_id opti621_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct pci_driver opti621_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "Opti621_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .id_table = opti621_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .probe = opti621_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int __init opti621_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ide_pci_register_driver(&opti621_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void __exit opti621_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_unregister_driver(&opti621_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) module_init(opti621_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) module_exit(opti621_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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