Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 1997-1998	Mark Lord <mlord@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 1998		Eddie C. Dost <ecd@skynet.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DRV_NAME "ns87415"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #ifdef CONFIG_SUPERIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * which use the integrated NS87514 cell for CD-ROM support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * i.e we have to support for CD-ROM installs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * See drivers/parisc/superio.c for more gory details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/superio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SUPERIO_IDE_MAX_RETRIES 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Because of a defect in Super I/O, all reads of the PCI DMA status 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * registers, IDE status register and the IDE select register need to be 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * retried
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static u8 superio_ide_inb (unsigned long port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int retries = SUPERIO_IDE_MAX_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* printk(" [ reading port 0x%x with retry ] ", port); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		tmp = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		if (tmp == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	} while (tmp == 0 && retries-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static u8 superio_read_status(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return superio_ide_inb(hwif->io_ports.status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static void superio_tf_read(ide_drive_t *drive, struct ide_taskfile *tf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			    u8 valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	if (valid & IDE_VALID_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		tf->error  = inb(io_ports->feature_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (valid & IDE_VALID_NSECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		tf->nsect  = inb(io_ports->nsect_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (valid & IDE_VALID_LBAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		tf->lbal   = inb(io_ports->lbal_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	if (valid & IDE_VALID_LBAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		tf->lbam   = inb(io_ports->lbam_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (valid & IDE_VALID_LBAH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		tf->lbah   = inb(io_ports->lbah_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (valid & IDE_VALID_DEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		tf->device = superio_ide_inb(io_ports->device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static void ns87415_dev_select(ide_drive_t *drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static const struct ide_tp_ops superio_tp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.exec_command		= ide_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.read_status		= superio_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.read_altstatus		= ide_read_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.write_devctl		= ide_write_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.dev_select		= ns87415_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.tf_load		= ide_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.tf_read		= superio_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.input_data		= ide_input_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.output_data		= ide_output_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void superio_init_iops(struct hwif_s *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 port = hwif->channel, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Clear error/interrupt, enable dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tmp = superio_ide_inb(dma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	outb(tmp | 0x66, dma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define superio_dma_sff_read_status ide_dma_sff_read_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * the IRQ associated with the port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * and selects either PIO or DMA handshaking for the next I/O operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	new = *old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* Adjust IRQ enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	bit = 1 << (8 + hwif->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (drive->dev_flags & IDE_DFLAG_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		new &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		new |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (new != *old) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		unsigned char stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		 * Don't change DMA engine settings while Write Buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		 * are busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		(void) pci_read_config_byte(dev, 0x43, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		while (stat & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			(void) pci_read_config_byte(dev, 0x43, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*old = new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		(void) pci_write_config_dword(dev, 0x40, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		 * And let things settle...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void ns87415_dev_select(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ns87415_prepare_drive(drive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			      !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void ns87415_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ns87415_prepare_drive(drive, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ns87415_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u8 dma_stat = 0, dma_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* get DMA command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	/* stop DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* from ERRATA: clear the INTR & ERROR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ns87415_prepare_drive(drive, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* verify good DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return (dma_stat & 7) != 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void init_hwif_ns87415 (ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	unsigned int ctrl, using_inta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u8 progif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef __sparc_v9__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u8 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Also, leave IRQ masked during drive probing, to prevent infinite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * interrupts from a potentially floating INTA..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * IRQs get unmasked in dev_select() when drive is first used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	(void) pci_read_config_dword(dev, 0x40, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	(void) pci_read_config_byte(dev, 0x09, &progif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* is irq in "native" mode? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	using_inta = progif & (1 << (hwif->channel << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!using_inta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		using_inta = ctrl & (1 << (4 + hwif->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (hwif->mate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		hwif->select_data = hwif->mate->select_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		hwif->select_data = (unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					&ns87415_control[ns87415_count++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (using_inta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			ctrl &= ~(1 << 6);	/* unmask INTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		*((unsigned int *)hwif->select_data) = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		(void) pci_write_config_dword(dev, 0x40, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		 * Set prefetch size to 512 bytes for both ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		 * but don't turn on/off prefetching here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		pci_write_config_byte(dev, 0x55, 0xee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifdef __sparc_v9__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		 * XXX: Reset the device, if we don't it will not respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		 *      dev_select() properly during first ide_probe_port().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		outb(12, hwif->io_ports.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		outb(8, hwif->io_ports.ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			stat = hwif->tp_ops->read_status(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			if (stat == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		} while ((stat & ATA_BUSY) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (!using_inta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (!hwif->dma_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct ide_tp_ops ns87415_tp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.exec_command		= ide_exec_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.read_status		= ide_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.read_altstatus		= ide_read_altstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.write_devctl		= ide_write_devctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.dev_select		= ns87415_dev_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.tf_load		= ide_tf_load,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.tf_read		= ide_tf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.input_data		= ide_input_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.output_data		= ide_output_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const struct ide_dma_ops ns87415_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.dma_host_set		= ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.dma_setup		= ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.dma_start		= ns87415_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.dma_end		= ns87415_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.dma_test_irq		= ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.dma_lost_irq		= ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.dma_sff_read_status	= superio_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct ide_port_info ns87415_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.init_hwif	= init_hwif_ns87415,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.tp_ops 	= &ns87415_tp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.dma_ops	= &ns87415_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			  IDE_HFLAG_NO_ATAPI_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct ide_port_info d = ns87415_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_SUPERIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (PCI_SLOT(dev->devfn) == 0xE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		/* Built-in - assume it's under superio. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		d.init_iops = superio_init_iops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		d.tp_ops = &superio_tp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct pci_device_id ns87415_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct pci_driver ns87415_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.name		= "NS87415_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.id_table	= ns87415_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.probe		= ns87415_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __init ns87415_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return ide_pci_register_driver(&ns87415_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void __exit ns87415_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	pci_unregister_driver(&ns87415_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) module_init(ns87415_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) module_exit(ns87415_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_LICENSE("GPL");