^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2004 Red Hat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based in part on the ITE vendor provided SCSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Datasheet is freely available, some other documents under NDA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The ITE8212 isn't exactly a standard IDE controller. It has two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * modes. In pass through mode then it is an IDE controller. In its smart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * mode its actually quite a capable hardware raid controller disguised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * as an IDE controller. Smart mode only understands DMA read/write and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * identify, none of the fancier commands apply. The IT8211 is identical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * in other respects but lacks the raid mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Errata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * o Rev 0x10 also requires master/slave hold the same DMA timings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * cannot do ATAPI MWDMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * o The identify data for raid volumes lacks CHS info (technically ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * but also fails to set the LBA28 and other bits. We fix these in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * the IDE probe quirk code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * raid then the controller firmware dies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * o Smart mode without RAID doesn't clear all the necessary identify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * bits to reduce the command set to the one used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This has a few impacts on the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - In pass through mode we do all the work you would expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - In smart mode the clocking set up is done by the controller generally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * but we must watch the other limits and filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - There are a few extra vendor commands that actually talk to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * controller but only work PIO with no IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Vendor areas of the identify block in smart mode are used for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * timing and policy set up. Each HDD in raid mode also has a serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * block on the disk. The hardware extra commands are get/set chip status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * rebuild, get rebuild status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * In Linux the driver supports pass through mode as if the device was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * just another IDE controller. If the smart mode is running then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * volumes are managed by the controller firmware and each IDE "disk"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * is a raid volume. Even more cute - the controller can do automated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * hotplug and rebuild.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * The pass through controller itself is a little demented. It has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * flaw that it has a single set of PIO/MWDMA timings per channel so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * non UDMA devices restrict each others performance. It also has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * single clock source per channel so mixed UDMA100/133 performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * isn't perfect and we have to pick a clock. Thankfully none of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * matters in smart mode. ATAPI DMA is not currently supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * - ATAPI UDMA is ok but not MWDMA it seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * - RAID configuration ioctls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * - Move to libata once it grows up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DRV_NAME "it821x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QUIRK_VORTEX86 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct it821x_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int smart:1, /* Are we in smart raid mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) timing10:1; /* Rev 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 clock_mode; /* 0, ATA_50 or ATA_66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 want[2][2]; /* Mode/Pri log for master slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* We need these for switching the clock when DMA goes on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) The high byte is the 66Mhz timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 pio[2]; /* Cached PIO values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 mwdma[2]; /* Cached MWDMA values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 udma[2]; /* Cached UDMA values (per drive) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ATA_66 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ATA_50 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ATA_ANY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define UDMA_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MWDMA_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * We allow users to force the card into non raid mode without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * flashing the alternative BIOS. This is also necessary right now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * for embedded platforms that cannot run a PC BIOS but are using this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int it8212_noraid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * it821x_program - program the PIO/MWDMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @drive: drive to tune
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @timing: timing info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Program the PIO/MWDMA timing for this channel according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * current clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void it821x_program(ide_drive_t *drive, u16 timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int channel = hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Program PIO/MWDMA timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if(itdev->clock_mode == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) conf = timing >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) conf = timing & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * it821x_program_udma - program the UDMA registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @drive: drive to tune
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @timing: timing info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Program the UDMA timing for this drive according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * current clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void it821x_program_udma(ide_drive_t *drive, u16 timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int channel = hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 unit = drive->dn & 1, conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Program UDMA timing bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if(itdev->clock_mode == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) conf = timing >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) conf = timing & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (itdev->timing10 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * it821x_clock_strategy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @drive: drive to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Select between the 50 and 66Mhz base clocks to get the best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * results for this interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void it821x_clock_strategy(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int clock, altclock, sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 unit = drive->dn & 1, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if(itdev->want[0][0] > itdev->want[1][0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clock = itdev->want[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) altclock = itdev->want[1][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clock = itdev->want[1][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) altclock = itdev->want[0][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * if both clocks can be used for the mode with the higher priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * use the clock needed by the mode with the lower priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (clock == ATA_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clock = altclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Nobody cares - keep the same clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if(clock == ATA_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* No change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if(clock == itdev->clock_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Load this into the controller ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if(clock == ATA_66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) itdev->clock_mode = ATA_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) itdev->clock_mode = ATA_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pci_read_config_byte(dev, 0x50, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) v &= ~(1 << (1 + hwif->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) v |= sel << (1 + hwif->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pci_write_config_byte(dev, 0x50, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Reprogram the UDMA/PIO of the pair drive for the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * MWDMA will be dealt with by the dma switcher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if(pair && itdev->udma[1-unit] != UDMA_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) it821x_program_udma(pair, itdev->udma[1-unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) it821x_program(pair, itdev->pio[1-unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Reprogram the UDMA/PIO of our drive for the switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * MWDMA will be dealt with by the dma switcher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if(itdev->udma[unit] != UDMA_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) it821x_program_udma(drive, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) it821x_program(drive, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * it821x_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Tune the host to the desired PIO mode taking into the consideration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * the maximum PIO mode supported by the other device on the cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void it821x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u8 unit = drive->dn & 1, set_pio = pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Spec says 89 ref driver uses 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Compute the best PIO mode we can for a given device. We must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * pick a speed that does not cause problems with the other device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * on the cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 pair_pio = pair->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* trim PIO to the slowest of the master/slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (pair_pio < set_pio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) set_pio = pair_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) itdev->want[unit][1] = pio_want[set_pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) itdev->want[unit][0] = 1; /* PIO is lowest priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) itdev->pio[unit] = pio_timings[set_pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) it821x_clock_strategy(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) it821x_program(drive, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * it821x_tune_mwdma - tune a channel for MWDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @drive: drive to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @mode_wanted: the target operating mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Load the timing settings for this device mode into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * controller when doing MWDMA in pass through mode. The caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * must manage the whole lack of per device MWDMA/PIO timings and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * the shared MWDMA/PIO timing register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void it821x_tune_mwdma(ide_drive_t *drive, u8 mode_wanted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u8 unit = drive->dn & 1, channel = hwif->channel, conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) itdev->want[unit][1] = mwdma_want[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) itdev->want[unit][0] = 2; /* MWDMA is low priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) itdev->mwdma[unit] = dma[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) itdev->udma[unit] = UDMA_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* UDMA bits off - Revision 0x10 do them in pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_read_config_byte(dev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) conf |= channel ? 0x60: 0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) conf |= 1 << (3 + 2 * channel + unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pci_write_config_byte(dev, 0x50, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) it821x_clock_strategy(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* FIXME: do we need to program this ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* it821x_program(drive, itdev->mwdma[unit]); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * it821x_tune_udma - tune a channel for UDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @drive: drive to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @mode_wanted: the target operating mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Load the timing settings for this device mode into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * controller when doing UDMA modes in pass through.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void it821x_tune_udma(ide_drive_t *drive, u8 mode_wanted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 unit = drive->dn & 1, channel = hwif->channel, conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) itdev->want[unit][1] = udma_want[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) itdev->want[unit][0] = 3; /* UDMA is high priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) itdev->mwdma[unit] = MWDMA_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) itdev->udma[unit] = udma[mode_wanted];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if(mode_wanted >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* UDMA on. Again revision 0x10 must do the pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pci_read_config_byte(dev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) conf &= channel ? 0x9F: 0xE7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) conf &= ~ (1 << (3 + 2 * channel + unit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pci_write_config_byte(dev, 0x50, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) it821x_clock_strategy(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) it821x_program_udma(drive, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * it821x_dma_read - DMA hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @drive: drive for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * The IT821x has a single timing register for MWDMA and for PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * operations. As we flip back and forth we have to reload the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * clock. In addition the rev 0x10 device only works if the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * timing value is loaded into the master and slave UDMA clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * so we must also reload that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * FIXME: we could figure out in advance if we need to do reloads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void it821x_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u8 unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if(itdev->mwdma[unit] != MWDMA_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) it821x_program(drive, itdev->mwdma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) it821x_program_udma(drive, itdev->udma[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * it821x_dma_write - DMA hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @drive: drive for DMA stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * The IT821x has a single timing register for MWDMA and for PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * operations. As we flip back and forth we have to reload the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int it821x_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct it821x_dev *itdev = ide_get_hwifdata(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int ret = ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if(itdev->mwdma[unit] != MWDMA_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) it821x_program(drive, itdev->pio[unit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * it821x_set_dma_mode - set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Tune the ITE chipset for the desired DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void it821x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * MWDMA tuning is really hard because our MWDMA and PIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * timings are kept in the same place. We can switch in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * host dma on/off callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) it821x_tune_udma(drive, speed - XFER_UDMA_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * it821x_cable_detect - cable detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @hwif: interface to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * Check for the presence of an ATA66 capable cable on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * interface. Problematic as it seems some cards don't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * the needed logic onboard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static u8 it821x_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* The reference driver also only does disk side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * it821x_quirkproc - post init callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * This callback is run after the drive has been probed but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * before anything gets attached. It allows drivers to do any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * final tuning that is needed, or fixups to work around bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void it821x_quirkproc(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u16 *id = drive->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!itdev->smart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * If we are in pass through mode then not much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * needs to be done, but we do bother to clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * IRQ mask as we may well be in PIO (eg rev 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * for now and we know unmasking is safe on this chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) drive->dev_flags |= IDE_DFLAG_UNMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Perform fixups on smart mode. We need to "lose" some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * capabilities the firmware lacks but does not filter, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * also patch up some capability bits that it forgets to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * in RAID mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Check for RAID v native */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (strstr((char *)&id[ATA_ID_PROD],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "Integrated Technology Express")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* In raid mode the ident block is slightly buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) We need to set the bits so that the IDE layer knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) LBA28. LBA48 and DMA ar valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Reporting logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) drive->name, id[147] ? "Bootable " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) id[ATA_ID_CSFO]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (id[ATA_ID_CSFO] != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) printk(KERN_CONT "(%dK stripe)", id[146]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) printk(KERN_CONT ".\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Non RAID volume. Fixups to stop the core code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) doing unsupported things */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) id[ATA_ID_FIELD_VALID] &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) id[ATA_ID_QUEUE_DEPTH] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) id[ATA_ID_COMMAND_SET_1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) id[ATA_ID_COMMAND_SET_2] &= 0xC400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) id[ATA_ID_CFSSE] &= 0xC000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) id[ATA_ID_CFS_ENABLE_1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) id[ATA_ID_CFS_ENABLE_2] &= 0xC400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) id[ATA_ID_CSF_DEFAULT] &= 0xC000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) id[127] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) id[ATA_ID_DLF] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) id[ATA_ID_CSFO] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) id[ATA_ID_CFA_POWER] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) printk(KERN_INFO "%s: Performing identify fixups.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Set MWDMA0 mode as enabled/support - just to tell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * IDE core that DMA is supported (it821x hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * takes care of DMA mode programming).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ata_id_has_dma(id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) id[ATA_ID_MWDMA_MODES] |= 0x0101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) drive->current_speed = XFER_MW_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct ide_dma_ops it821x_pass_through_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .dma_start = it821x_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .dma_end = it821x_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .dma_test_irq = ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * init_hwif_it821x - set up hwif structs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * @hwif: interface to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * We do the basic set up of the interface structure. The IT8212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * requires several custom handlers so we override the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * ide DMA handlers appropriately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void init_hwif_it821x(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct it821x_dev *itdevs = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct it821x_dev *idev = itdevs + hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ide_set_hwifdata(hwif, idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pci_read_config_byte(dev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (conf & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) idev->smart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Long I/O's although allowed in LBA48 space cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) onboard firmware to enter the twighlight zone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hwif->rqsize = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Pull the current clocks from 0x50 also */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (conf & (1 << (1 + hwif->channel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) idev->clock_mode = ATA_50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) idev->clock_mode = ATA_66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) idev->want[0][1] = ATA_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) idev->want[1][1] = ATA_ANY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * Not in the docs but according to the reference driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * this is necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (dev->revision == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) idev->timing10 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (idev->smart == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "workarounds activated\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (idev->smart == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* MWDMA/PIO clock switching for pass through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) hwif->dma_ops = &it821x_pass_through_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (hwif->dma_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) hwif->ultra_mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) hwif->mwdma_mask = ATA_MWDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Vortex86SX quirk: prevent Ultra-DMA mode to fix BadCRC issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (idev->quirks & QUIRK_VORTEX86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (dev->revision == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) hwif->ultra_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void it8212_disable_raid(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Reset local CPU, and set BIOS not ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pci_write_config_byte(dev, 0x5E, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Set to bypass mode, and reset PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pci_write_config_byte(dev, 0x50, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pci_write_config_word(dev, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PCI_COMMAND_PARITY | PCI_COMMAND_IO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pci_write_config_word(dev, 0x40, 0xA0F3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) pci_write_config_dword(dev,0x4C, 0x02040204);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pci_write_config_byte(dev, 0x42, 0x36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int init_chipset_it821x(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u8 conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static char *mode[2] = { "pass through", "smart" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Force the card into bypass mode if so requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (it8212_noraid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) it8212_disable_raid(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pci_read_config_byte(dev, 0x50, &conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pci_name(dev), mode[conf & 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct ide_port_ops it821x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .set_pio_mode = it821x_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .set_dma_mode = it821x_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .quirkproc = it821x_quirkproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .cable_detect = it821x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const struct ide_port_info it821x_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .init_chipset = init_chipset_it821x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .init_hwif = init_hwif_it821x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .port_ops = &it821x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * it821x_init_one - pci layer discovery entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * @id: ident table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * Called by the PCI code when it finds an ITE821x controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * We then use the IDE PCI generic helper to do most of the work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct it821x_dev *itdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) itdevs = kcalloc(2, sizeof(*itdevs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (itdevs == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) itdevs->quirks = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) kfree(itdevs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void it821x_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct it821x_dev *itdevs = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) kfree(itdevs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const struct pci_device_id it821x_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), QUIRK_VORTEX86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static struct pci_driver it821x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .name = "ITE821x IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .id_table = it821x_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .probe = it821x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .remove = it821x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int __init it821x_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return ide_pci_register_driver(&it821x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void __exit it821x_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) pci_unregister_driver(&it821x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) module_init(it821x_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) module_exit(it821x_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) module_param_named(noraid, it8212_noraid, int, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) MODULE_PARM_DESC(noraid, "Force card into bypass mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) MODULE_AUTHOR("Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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