^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ITE 8213 IDE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Jack Lee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Alan Cox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRV_NAME "it8213"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * it8213_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Set the interface PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void it8213_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int is_slave = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int master_port = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int slave_port = 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 master_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 slave_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static DEFINE_SPINLOCK(tune_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const u8 timings[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 2, 3 }, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spin_lock_irqsave(&tune_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pci_read_config_word(dev, master_port, &master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) control |= 1; /* Programmable timing on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (drive->media != ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) control |= 4; /* ATAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ide_pio_need_iordy(drive, pio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) control |= 2; /* IORDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (is_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) master_data |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) master_data &= ~0x0070;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) master_data = master_data | (control << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_read_config_byte(dev, slave_port, &slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) slave_data = slave_data & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) slave_data = slave_data | (timings[pio][0] << 2) | timings[pio][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) master_data &= ~0x3307;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (pio > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) master_data = master_data | control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pci_write_config_word(dev, master_port, master_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pci_write_config_byte(dev, slave_port, slave_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spin_unlock_irqrestore(&tune_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * it8213_set_dma_mode - set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Tune the ITE chipset for the DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void it8213_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 maslave = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int a_speed = 3 << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int u_flag = 1 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int v_flag = 0x01 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int w_flag = 0x10 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int u_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 reg4042, reg4a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 reg48, reg54, reg55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pci_read_config_word(dev, maslave, ®4042);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_read_config_byte(dev, 0x48, ®48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_read_config_word(dev, 0x4a, ®4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pci_read_config_byte(dev, 0x54, ®54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pci_read_config_byte(dev, 0x55, ®55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 udma = speed - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!(reg48 & u_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_write_config_byte(dev, 0x48, reg48 | u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (speed >= XFER_UDMA_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if ((reg4a & a_speed) != u_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (speed > XFER_UDMA_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!(reg54 & v_flag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pci_write_config_byte(dev, 0x54, reg54 | v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const u8 mwdma_to_pio[] = { 0, 3, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (reg48 & u_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (reg4a & a_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (reg54 & v_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (reg55 & w_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (speed >= XFER_MW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) drive->pio_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) it8213_set_pio_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static u8 it8213_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 reg42h = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_read_config_byte(dev, 0x42, ®42h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return (reg42h & 0x02) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct ide_port_ops it8213_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_pio_mode = it8213_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_dma_mode = it8213_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .cable_detect = it8213_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct ide_port_info it8213_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .enablebits = { {0x41, 0x80, 0x80} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .port_ops = &it8213_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .host_flags = IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .swdma_mask = ATA_SWDMA2_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .mwdma_mask = ATA_MWDMA12_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .udma_mask = ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * it8213_init_one - pci layer discovery entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @id: ident table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Called by the PCI code when it finds an ITE8213 controller. As
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * this device follows the standard interfaces we can use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * standard helper functions to do almost all the work for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int it8213_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ide_pci_init_one(dev, &it8213_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct pci_device_id it8213_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct pci_driver it8213_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "ITE8213_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .id_table = it8213_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .probe = it8213_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int __init it8213_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ide_pci_register_driver(&it8213_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void __exit it8213_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci_unregister_driver(&it8213_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) module_init(it8213_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) module_exit(it8213_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_AUTHOR("Jack Lee, Alan Cox");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_DESCRIPTION("PCI driver module for the ITE 8213");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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