^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BRIEF MODULE DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * IT8172 IDE controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000 MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Shane McDonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Free Software Foundation; either version 2 of the License, or (at your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * You should have received a copy of the GNU General Public License along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * with this program; if not, write to the Free Software Foundation, Inc.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRV_NAME "IT8172"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void it8172_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 drive_enables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 drive_timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * The highest value of DIOR/DIOW pulse width and recovery time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * that can be set in the IT8172 is 8 PCI clock cycles. As a result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * it cannot be configured for PIO mode 0. This table sets these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * parameters to the maximum supported by the IT8172.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const u8 timings[] = { 0x3f, 0x3c, 0x1b, 0x12, 0x0a };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pci_read_config_word(dev, 0x40, &drive_enables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pci_read_config_dword(dev, 0x44, &drive_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Enable port 0x44. The IT8172 spec is confused; it calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * this register the "Slave IDE Timing Register", but in fact,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * it controls timing for both master and slave drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) drive_enables |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) drive_enables &= drive->dn ? 0xc006 : 0xc060;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (drive->media == ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* enable prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) drive_enables |= 0x0004 << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ide_pio_need_iordy(drive, pio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* enable IORDY sample-point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) drive_enables |= 0x0002 << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) drive_timing &= drive->dn ? 0x00003f00 : 0x000fc000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) drive_timing |= timings[pio] << (drive->dn * 6 + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pci_write_config_word(dev, 0x40, drive_enables);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci_write_config_dword(dev, 0x44, drive_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void it8172_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int a_speed = 3 << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int u_flag = 1 << drive->dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int u_speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 reg48, reg4a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci_read_config_byte(dev, 0x48, ®48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pci_read_config_byte(dev, 0x4a, ®4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 udma = speed - XFER_UDMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u_speed = udma << (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pci_write_config_byte(dev, 0x48, reg48 | u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) reg4a &= ~a_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const u8 mwdma_to_pio[] = { 0, 3, 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) drive->pio_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) it8172_set_pio_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct ide_port_ops it8172_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .set_pio_mode = it8172_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .set_dma_mode = it8172_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const struct ide_port_info it8172_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .port_ops = &it8172_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .enablebits = { {0x41, 0x80, 0x80}, {0x00, 0x00, 0x00} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .host_flags = IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .pio_mask = ATA_PIO4 & ~ATA_PIO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENODEV; /* IT8172 is more than an IDE controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ide_pci_init_one(dev, &it8172_port_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct pci_device_id it8172_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8172), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct pci_driver it8172_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "IT8172_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .id_table = it8172_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .probe = it8172_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __init it8172_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ide_pci_register_driver(&it8172_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void __exit it8172_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_unregister_driver(&it8172_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module_init(it8172_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module_exit(it8172_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_AUTHOR("Steve Longerbeam");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags