Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  *  Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Portions (C) Copyright 2002  Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * under the terms of the GNU General Public License as published by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Free Software Foundation; either version 2, or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This program is distributed in the hope that it will be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * For the avoidance of doubt the "preferred form" of this code is one which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * is in an open non patent encumbered format. Where cryptographic key signing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * forms part of the process of creating an executable the information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * including keys needed to generate an equivalently functional executable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * are deemed to be part of the source code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRV_NAME "ide_pci_generic"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static bool ide_generic_all;		/* Set to claim all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_param_named(all_generic_ide, ide_generic_all, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE storage controllers.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static void netcell_quirkproc(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* mark words 85-87 as valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	drive->id[ATA_ID_CSF_DEFAULT] |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static const struct ide_port_ops netcell_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.quirkproc		= netcell_quirkproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DECLARE_GENERIC_PCI_DEV(extra_flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.name		= DRV_NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				  extra_flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.swdma_mask	= ATA_SWDMA2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.mwdma_mask	= ATA_MWDMA2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.udma_mask	= ATA_UDMA6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static const struct ide_port_info generic_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/*  0: Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	DECLARE_GENERIC_PCI_DEV(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{	/* 1: NS87410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.enablebits	= { {0x43, 0x08, 0x08}, {0x47, 0x08, 0x08} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.swdma_mask	= ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.udma_mask	= ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/*  2: SAMURAI / HT6565 / HINT_IDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	DECLARE_GENERIC_PCI_DEV(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/*  3: UM8673F / UM8886A / UM8886BF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	DECLARE_GENERIC_PCI_DEV(IDE_HFLAG_NO_DMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/*  4: VIA_IDE / OPTI621V / Piccolo010{2,3,5} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	DECLARE_GENERIC_PCI_DEV(IDE_HFLAG_NO_AUTODMA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{	/* 5: VIA8237SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.swdma_mask	= ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.udma_mask	= ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{	/* 6: Revolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.port_ops	= &netcell_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				  IDE_HFLAG_TRUST_BIOS_FOR_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.swdma_mask	= ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.udma_mask	= ATA_UDMA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	generic_init_one	-	called when a PIIX is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  *	@dev: the generic device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  *	@id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  *	Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  *	finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	const struct ide_port_info *d = &generic_chipsets[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	/* Don't use the generic entry unless instructed to do so */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (id->driver_data == 0 && ide_generic_all == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	switch (dev->vendor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case PCI_VENDOR_ID_UMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		if (dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				!(PCI_FUNC(dev->devfn) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			goto out; /* UM8886A/BF pair */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	case PCI_VENDOR_ID_OPTI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				!(PCI_FUNC(dev->devfn) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case PCI_VENDOR_ID_JMICRON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (dev->device != PCI_DEVICE_ID_JMICRON_JMB368 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				PCI_FUNC(dev->devfn) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case PCI_VENDOR_ID_NS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (dev->device == PCI_DEVICE_ID_NS_87410 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				(dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (dev->vendor != PCI_VENDOR_ID_JMICRON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		u16 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		pci_read_config_word(dev, PCI_COMMAND, &command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		if (!(command & PCI_COMMAND_IO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			printk(KERN_INFO "%s %s: skipping disabled "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				"controller\n", d->name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ret = ide_pci_init_one(dev, d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct pci_device_id generic_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ PCI_VDEVICE(NS,	PCI_DEVICE_ID_NS_87410),		 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ PCI_VDEVICE(PCTECH,	PCI_DEVICE_ID_PCTECH_SAMURAI_IDE),	 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ PCI_VDEVICE(HOLTEK,	PCI_DEVICE_ID_HOLTEK_6565),		 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ PCI_VDEVICE(UMC,	PCI_DEVICE_ID_UMC_UM8673F),		 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ PCI_VDEVICE(UMC,	PCI_DEVICE_ID_UMC_UM8886A),		 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ PCI_VDEVICE(UMC,	PCI_DEVICE_ID_UMC_UM8886BF),		 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ PCI_VDEVICE(HINT,	PCI_DEVICE_ID_HINT_VXPROII_IDE),	 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ PCI_VDEVICE(VIA,	PCI_DEVICE_ID_VIA_82C561),		 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ PCI_VDEVICE(OPTI,	PCI_DEVICE_ID_OPTI_82C558),		 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ PCI_VDEVICE(VIA,	PCI_DEVICE_ID_VIA_8237_SATA),		 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ PCI_VDEVICE(TOSHIBA,	PCI_DEVICE_ID_TOSHIBA_PICCOLO_1),	 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{ PCI_VDEVICE(TOSHIBA,	PCI_DEVICE_ID_TOSHIBA_PICCOLO_2),	 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	{ PCI_VDEVICE(TOSHIBA,	PCI_DEVICE_ID_TOSHIBA_PICCOLO_3),	 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	{ PCI_VDEVICE(TOSHIBA,	PCI_DEVICE_ID_TOSHIBA_PICCOLO_5),	 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	{ PCI_VDEVICE(NETCELL,	PCI_DEVICE_ID_REVOLUTION),		 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * Must come last.  If you add entries adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * this table and generic_chipsets[] appropriately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MODULE_DEVICE_TABLE(pci, generic_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct pci_driver generic_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.name		= "PCI_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.id_table	= generic_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.probe		= generic_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int __init generic_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return ide_pci_register_driver(&generic_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void __exit generic_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	pci_unregister_driver(&generic_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) module_init(generic_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) module_exit(generic_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_AUTHOR("Andre Hedrick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_DESCRIPTION("PCI driver module for generic PCI IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MODULE_LICENSE("GPL");