^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * IDE DMA support (including IDE PCI BM-DMA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1995-1998 Mark Lord
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004, 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Special Thanks to Mark for his Six years of work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * fixing the problem with the BIOS on some Acer motherboards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * "TX" chipset compatibility and for providing patches for the "TX" chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * at generic DMA -- his patches were referred to when preparing this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * for supplying a Promise UDMA board & WD UDMA drive for this work!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct drive_list_entry drive_whitelist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "Micropolis 2112A" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { "CONNER CTMA 4000" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "CONNER CTT8000-A" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "ST34342A" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { NULL , NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct drive_list_entry drive_blacklist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "WDC AC11000H" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "WDC AC22100H" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { "WDC AC32500H" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { "WDC AC33100H" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { "WDC AC31600H" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "WDC AC32100H" , "24.09P07" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "WDC AC23200L" , "21.10N21" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "Compaq CRD-8241B" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "CRD-8400B" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { "CRD-8480B", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "CRD-8482B", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { "CRD-84" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { "SanDisk SDP3B" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { "SanDisk SDP3B-64" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "SANYO CD-ROM CRD" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { "HITACHI CDR-8" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { "HITACHI CDR-8335" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { "HITACHI CDR-8435" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { "Toshiba CD-ROM XM-6202B" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "TOSHIBA CD-ROM XM-1702BC", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { "CD-532E-A" , NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { "E-IDE CD-ROM CR-840", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { "CD-ROM Drive/F5A", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { "WPI CDD-820", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "SAMSUNG CD-ROM SC-148C", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { "SAMSUNG CD-ROM SC", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "_NEC DV5800A", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "SAMSUNG CD-ROM SN-124", "N001" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "Seagate STT20000A", NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "CD-ROM CDR_U200", "1.09" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { NULL , NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * ide_dma_intr - IDE DMA interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @drive: the drive the interrupt is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Handle an interrupt completing a read/write DMA transfer on an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * IDE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ide_startstop_t ide_dma_intr(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ide_cmd *cmd = &hwif->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 stat = 0, dma_stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) drive->waiting_for_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_stat = hwif->dma_ops->dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ide_dma_unmap_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) stat = hwif->tp_ops->read_status(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!dma_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if ((cmd->tf_flags & IDE_TFLAG_FS) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ide_finish_cmd(drive, cmd, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ide_complete_rq(drive, BLK_STS_OK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) blk_rq_sectors(cmd->rq) << 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ide_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) printk(KERN_ERR "%s: %s: bad DMA status (0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) drive->name, __func__, dma_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ide_error(drive, "dma_intr", stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ide_dma_good_drive(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ide_in_drive_list(drive->id, drive_whitelist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * ide_dma_map_sg - map IDE scatter gather for DMA I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @drive: the drive to map the DMA table for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @cmd: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Perform the DMA mapping magic necessary to access the source or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * target buffers of a request via DMA. The lower layers of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * kernel provide the necessary cache management so that we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * operate in a portable fashion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int ide_dma_map_sg(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct scatterlist *sg = hwif->sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (cmd->tf_flags & IDE_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cmd->sg_dma_direction = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cmd->sg_dma_direction = DMA_FROM_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) i = dma_map_sg(hwif->dev, sg, cmd->sg_nents, cmd->sg_dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cmd->orig_sg_nents = cmd->sg_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cmd->sg_nents = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * ide_dma_unmap_sg - clean up DMA mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @drive: The drive to unmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Teardown mappings after DMA has completed. This must be called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * after the completion of each use of ide_build_dmatable and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * the next use of ide_build_dmatable. Failure to do so will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * an oops as only one mapping can be live for each target at a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void ide_dma_unmap_sg(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dma_unmap_sg(hwif->dev, hwif->sg_table, cmd->orig_sg_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cmd->sg_dma_direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EXPORT_SYMBOL_GPL(ide_dma_unmap_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * ide_dma_off_quietly - Generic DMA kill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @drive: drive to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Turn off the current DMA on this IDE controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void ide_dma_off_quietly(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) drive->dev_flags &= ~IDE_DFLAG_USING_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) drive->hwif->dma_ops->dma_host_set(drive, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) EXPORT_SYMBOL(ide_dma_off_quietly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * ide_dma_off - disable DMA on a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @drive: drive to disable DMA on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Disable IDE DMA for a device on this IDE controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Inform the user that DMA has been disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void ide_dma_off(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) printk(KERN_INFO "%s: DMA disabled\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ide_dma_off_quietly(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EXPORT_SYMBOL(ide_dma_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * ide_dma_on - Enable DMA on a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @drive: drive to enable DMA on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Enable IDE DMA for a device on this IDE controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void ide_dma_on(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) drive->dev_flags |= IDE_DFLAG_USING_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) drive->hwif->dma_ops->dma_host_set(drive, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int __ide_dma_bad_drive(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u16 *id = drive->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int blacklist = ide_in_drive_list(id, drive_blacklist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (blacklist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) drive->name, (char *)&id[ATA_ID_PROD]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return blacklist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) EXPORT_SYMBOL(__ide_dma_bad_drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const u8 xfer_mode_bases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) XFER_UDMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) XFER_MW_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) XFER_SW_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u16 *id = drive->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const struct ide_port_ops *port_ops = hwif->port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case XFER_UDMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if ((id[ATA_ID_FIELD_VALID] & 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mask = id[ATA_ID_UDMA_MODES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (port_ops && port_ops->udma_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mask &= port_ops->udma_filter(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mask &= hwif->ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * avoid false cable warning from eighty_ninty_three()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (req_mode > XFER_UDMA_2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mask &= 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case XFER_MW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mask = id[ATA_ID_MWDMA_MODES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Also look for the CF specific MWDMA modes... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ata_id_is_cfa(id) && (id[ATA_ID_CFA_MODES] & 0x38)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u8 mode = ((id[ATA_ID_CFA_MODES] & 0x38) >> 3) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mask |= ((2 << mode) - 1) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (port_ops && port_ops->mdma_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mask &= port_ops->mdma_filter(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mask &= hwif->mwdma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case XFER_SW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mask = id[ATA_ID_SWDMA_MODES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (!(mask & ATA_SWDMA2) && (id[ATA_ID_OLD_DMA_MODES] >> 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * if the mode is valid convert it to the mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * (the maximum allowed mode is XFER_SW_DMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (mode <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mask = (2 << mode) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mask &= hwif->swdma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * ide_find_dma_mode - compute DMA speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @drive: IDE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @req_mode: requested mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Checks the drive/host capabilities and finds the speed to use for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * the DMA transfer. The speed is then limited by the requested mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Returns 0 if the drive/host combination is incapable of DMA transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * or if the requested mode is not a DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int x, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (drive->media != ide_disk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (req_mode < xfer_mode_bases[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) x = fls(mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (x >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mode = xfer_mode_bases[i] + x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (hwif->chipset == ide_acorn && mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * is this correct?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ide_dma_good_drive(drive) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) drive->id[ATA_ID_EIDE_DMA_TIME] < 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mode = XFER_MW_DMA_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mode = min(mode, req_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) printk(KERN_INFO "%s: %s mode selected\n", drive->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) mode ? ide_xfer_verbose(mode) : "no DMA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int ide_tune_dma(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ata_id_has_dma(drive->id) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (drive->dev_flags & IDE_DFLAG_NODMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* consult the list of known "bad" drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (__ide_dma_bad_drive(drive))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return config_drive_for_dma(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) speed = ide_max_dma_mode(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ide_set_dma_mode(drive, speed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int ide_dma_check(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ide_tune_dma(drive))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* TODO: always do PIO fallback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ide_set_max_pio(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ide_set_dma(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Force DMAing for the beginning of the check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Some chipsets appear to do interesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * things, if not checked and cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * PARANOIA!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ide_dma_off_quietly(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rc = ide_dma_check(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ide_dma_on(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void ide_check_dma_crc(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ide_dma_off_quietly(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) drive->crc_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mode = drive->current_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Don't try non Ultra-DMA modes without iCRC's. Force the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * device to PIO and make the user enable SWDMA/MWDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mode--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mode = XFER_PIO_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ide_set_xfer_rate(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (drive->current_speed >= XFER_SW_DMA_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ide_dma_on(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void ide_dma_lost_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) EXPORT_SYMBOL_GPL(ide_dma_lost_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * un-busy the port etc, and clear any pending DMA status. we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * retry the current request in pio mode instead of risking tossing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * all away
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const struct ide_dma_ops *dma_ops = hwif->dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct ide_cmd *cmd = &hwif->cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ide_startstop_t ret = ide_stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * end current dma transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) printk(KERN_WARNING "%s: DMA timeout error\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) drive->waiting_for_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) (void)dma_ops->dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ide_dma_unmap_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = ide_error(drive, "dma timeout error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) hwif->tp_ops->read_status(hwif));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) printk(KERN_WARNING "%s: DMA timeout retry\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dma_ops->dma_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dma_ops->dma_clear(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (dma_ops->dma_test_irq(drive) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ide_dump_status(drive, "DMA timeout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hwif->tp_ops->read_status(hwif));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) drive->waiting_for_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) (void)dma_ops->dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ide_dma_unmap_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * disable dma for now, but remember that we did so because of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * a timeout -- we'll reenable after we finish this next request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * (or rather the first chunk of it) in pio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) drive->dev_flags |= IDE_DFLAG_DMA_PIO_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) drive->retry_pio++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ide_dma_off_quietly(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * make sure request is sane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (hwif->rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) scsi_req(hwif->rq)->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) void ide_release_dma_engine(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (hwif->dmatable_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dma_free_coherent(hwif->dev, prd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) hwif->dmatable_cpu, hwif->dmatable_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) hwif->dmatable_cpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) EXPORT_SYMBOL_GPL(ide_release_dma_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ide_allocate_dma_engine(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int prd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (hwif->prd_max_nents == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hwif->prd_max_nents = PRD_ENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (hwif->prd_ent_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) hwif->prd_ent_size = PRD_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev, prd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &hwif->dmatable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (hwif->dmatable_cpu == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) printk(KERN_ERR "%s: unable to allocate PRD table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) hwif->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ide_dma_prepare(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct ide_dma_ops *dma_ops = drive->hwif->dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if ((drive->dev_flags & IDE_DFLAG_USING_DMA) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (dma_ops->dma_check && dma_ops->dma_check(drive, cmd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ide_map_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ide_dma_map_sg(drive, cmd) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto out_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (dma_ops->dma_setup(drive, cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto out_dma_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) drive->waiting_for_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) out_dma_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ide_dma_unmap_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) out_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ide_map_sg(drive, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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