^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 1996-2004 Russell King.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Please note that this platform does not support 32-bit IDE IO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/ecard.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "icside"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ICS_IDENT_OFFSET 0x2280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ICS_ARCIN_V5_INTRSTAT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ICS_ARCIN_V5_INTROFFSET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ICS_ARCIN_V5_IDEOFFSET 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ICS_ARCIN_V5_IDESTEPPING 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ICS_ARCIN_V6_IDESTEPPING 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct cardinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int dataoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int ctrloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int stepping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct cardinfo icside_cardinfo_v5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .dataoffset = ICS_ARCIN_V5_IDEOFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .stepping = ICS_ARCIN_V5_IDESTEPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static struct cardinfo icside_cardinfo_v6_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .stepping = ICS_ARCIN_V6_IDESTEPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct cardinfo icside_cardinfo_v6_2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .stepping = ICS_ARCIN_V6_IDESTEPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct icside_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *irq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *ioc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct ide_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ICS_TYPE_A3IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ICS_TYPE_A3USER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ICS_TYPE_V6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ICS_TYPE_V5 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ICS_TYPE_NOTYPE ((unsigned int)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ---------------- Version 5 PCB Support Functions --------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Purpose : enable interrupts from card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct icside_state *state = ec->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Purpose : disable interrupts from card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct icside_state *state = ec->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const expansioncard_ops_t icside_ops_arcin_v5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .irqenable = icside_irqenable_arcin_v5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .irqdisable = icside_irqdisable_arcin_v5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ---------------- Version 6 PCB Support Functions --------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Purpose : enable interrupts from card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct icside_state *state = ec->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *base = state->irq_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) state->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) switch (state->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) readb(base + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) readb(base + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Purpose : disable interrupts from card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct icside_state *state = ec->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) state->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Prototype: icside_irqprobe(struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Purpose : detect an active interrupt from card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int icside_irqpending_arcin_v6(struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct icside_state *state = ec->irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const expansioncard_ops_t icside_ops_arcin_v6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .irqenable = icside_irqenable_arcin_v6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .irqdisable = icside_irqdisable_arcin_v6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .irqpending = icside_irqpending_arcin_v6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Handle routing of interrupts. This is called before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * we write the command to the drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void icside_maskproc(ide_drive_t *drive, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct expansion_card *ec = ECARD_DEV(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct icside_state *state = ecard_get_drvdata(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) state->channel = hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (state->enabled && !mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) switch (hwif->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct ide_port_ops icside_v6_no_dma_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .maskproc = icside_maskproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * SG-DMA support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * There is only one DMA controller per card, which means that only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * one drive can be accessed at one time. NOTE! We do not enforce that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * here, but we rely on the main IDE driver spotting that both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * interfaces use the same IRQ, which should guarantee this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Configure the IOMD to give the appropriate timings for the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * mode being requested. We take the advice of the ATA standards, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * calculate the cycle time based on the transfer mode, and the EIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * MW DMA specs that the drive provides in the IDENTIFY command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * We have the following IOMD DMA modes to choose from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Type Active Recovery Cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * A 250 (250) 312 (550) 562 (800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * B 187 250 437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * C 125 (125) 125 (375) 250 (500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * D 62 125 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * (figures in brackets are actual measured timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * However, we also need to take care of the read/write active and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * recovery timings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Read Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * Mode Active -- Recovery -- Cycle IOMD type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * MW0 215 50 215 480 A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * MW1 80 50 50 150 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * MW2 70 25 25 120 C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void icside_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long cycle_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int use_dma_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) const u8 xfer_mode = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (xfer_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case XFER_MW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cycle_time = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) use_dma_info = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case XFER_MW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cycle_time = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) use_dma_info = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case XFER_MW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cycle_time = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case XFER_SW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case XFER_SW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case XFER_SW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cycle_time = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * take care to note the values in the ID...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (use_dma_info && drive->id[ATA_ID_EIDE_DMA_TIME] > cycle_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) cycle_time = drive->id[ATA_ID_EIDE_DMA_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ide_set_drivedata(drive, (void *)cycle_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) printk(KERN_INFO "%s: %s selected (peak %luMB/s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) drive->name, ide_xfer_verbose(xfer_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 2000 / (cycle_time ? cycle_time : (unsigned long) -1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct ide_port_ops icside_v6_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .set_dma_mode = icside_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .maskproc = icside_maskproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void icside_dma_host_set(ide_drive_t *drive, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int icside_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct expansion_card *ec = ECARD_DEV(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) disable_dma(ec->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return get_dma_residue(ec->dma) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void icside_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct expansion_card *ec = ECARD_DEV(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* We can not enable DMA on both channels simultaneously. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BUG_ON(dma_channel_active(ec->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) enable_dma(ec->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int icside_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct expansion_card *ec = ECARD_DEV(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct icside_state *state = ecard_get_drvdata(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (cmd->tf_flags & IDE_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dma_mode = DMA_MODE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dma_mode = DMA_MODE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * We can not enable DMA on both channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) BUG_ON(dma_channel_active(ec->dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Ensure that we have the right interrupt routed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) icside_maskproc(drive, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Route the DMA signals to the correct interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) writeb(state->sel | hwif->channel, state->ioc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Select the correct timing for this drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) set_dma_speed(ec->dma, (unsigned long)ide_get_drivedata(drive));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Tell the DMA engine about the SG table and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * data direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) set_dma_sg(ec->dma, hwif->sg_table, cmd->sg_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) set_dma_mode(ec->dma, dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int icside_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct expansion_card *ec = ECARD_DEV(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct icside_state *state = ecard_get_drvdata(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return readb(state->irq_port +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (hwif->channel ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ICS_ARCIN_V6_INTRSTAT_2 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ICS_ARCIN_V6_INTRSTAT_1)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int icside_dma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) hwif->dmatable_cpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) hwif->dmatable_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct ide_dma_ops icside_v6_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .dma_host_set = icside_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .dma_setup = icside_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .dma_start = icside_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .dma_end = icside_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .dma_test_irq = icside_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int icside_dma_off_init(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void icside_setup_ports(struct ide_hw *hw, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct cardinfo *info, struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long port = (unsigned long)base + info->dataoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hw->io_ports.data_addr = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) hw->io_ports.error_addr = port + (1 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hw->io_ports.nsect_addr = port + (2 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) hw->io_ports.lbal_addr = port + (3 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hw->io_ports.lbam_addr = port + (4 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hw->io_ports.lbah_addr = port + (5 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hw->io_ports.device_addr = port + (6 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hw->io_ports.status_addr = port + (7 << info->stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) hw->io_ports.ctl_addr = (unsigned long)base + info->ctrloffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) hw->irq = ec->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hw->dev = &ec->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct ide_port_info icside_v5_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .host_flags = IDE_HFLAG_NO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .chipset = ide_acorn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int icside_register_v5(struct icside_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ide_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct ide_hw hw, *hws[] = { &hw };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) state->irq_port = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ec->irqmask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ecard_setirq(ec, &icside_ops_arcin_v5, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Be on the safe side - disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) icside_irqdisable_arcin_v5(ec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) icside_setup_ports(&hw, base, &icside_cardinfo_v5, ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) host = ide_host_alloc(&icside_v5_port_info, hws, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (host == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) state->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ecard_set_drvdata(ec, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = ide_host_register(host, &icside_v5_port_info, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ide_host_free(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ecard_set_drvdata(ec, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct ide_port_info icside_v6_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .init_dma = icside_dma_off_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .port_ops = &icside_v6_no_dma_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .host_flags = IDE_HFLAG_SERIALIZE | IDE_HFLAG_MMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .swdma_mask = ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .chipset = ide_acorn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int icside_register_v6(struct icside_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) void __iomem *ioc_base, *easi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct ide_host *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct ide_hw hw[2], *hws[] = { &hw[0], &hw[1] };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct ide_port_info d = icside_v6_port_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!ioc_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) easi_base = ioc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!easi_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Enable access to the EASI region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sel = 1 << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) writeb(sel, ioc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ecard_setirq(ec, &icside_ops_arcin_v6, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) state->irq_port = easi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) state->ioc_base = ioc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) state->sel = sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Be on the safe side - disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) icside_irqdisable_arcin_v6(ec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) icside_setup_ports(&hw[0], easi_base, &icside_cardinfo_v6_1, ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) icside_setup_ports(&hw[1], easi_base, &icside_cardinfo_v6_2, ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) host = ide_host_alloc(&d, hws, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (host == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) state->host = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ecard_set_drvdata(ec, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) d.init_dma = icside_dma_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) d.port_ops = &icside_v6_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) d.dma_ops = &icside_v6_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = ide_host_register(host, &d, hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ide_host_free(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (d.dma_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) free_dma(ec->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ecard_set_drvdata(ec, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int icside_probe(struct expansion_card *ec, const struct ecard_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct icside_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void __iomem *idmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = ecard_request_resources(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) state = kzalloc(sizeof(struct icside_state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) state->type = ICS_TYPE_NOTYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (idmem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) type = readb(idmem + ICS_IDENT_OFFSET) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ecardm_iounmap(ec, idmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) state->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) switch (state->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case ICS_TYPE_A3IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_warn(&ec->dev, "A3IN unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case ICS_TYPE_A3USER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_warn(&ec->dev, "A3USER unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case ICS_TYPE_V5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = icside_register_v5(state, ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case ICS_TYPE_V6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = icside_register_v6(state, ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_warn(&ec->dev, "unknown interface type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ecard_release_resources(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void icside_remove(struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct icside_state *state = ecard_get_drvdata(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) switch (state->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case ICS_TYPE_V5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* FIXME: tell IDE to stop using the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) icside_irqdisable_arcin_v5(ec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case ICS_TYPE_V6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* FIXME: tell IDE to stop using the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ec->dma != NO_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) free_dma(ec->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) icside_irqdisable_arcin_v6(ec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Reset the ROM pointer/EASI selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writeb(0, state->ioc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ecard_set_drvdata(ec, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) kfree(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ecard_release_resources(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static void icside_shutdown(struct expansion_card *ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct icside_state *state = ecard_get_drvdata(ec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * Disable interrupts from this card. We need to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * this before disabling EASI since we may be accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * this register via that region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ec->ops->irqdisable(ec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * Reset the ROM pointer so that we can read the ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * after a soft reboot. This also disables access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * the IDE taskfile via the EASI region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (state->ioc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) writeb(0, state->ioc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct ecard_id icside_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { MANU_ICS, PROD_ICS_IDE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { MANU_ICS2, PROD_ICS2_IDE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { 0xffff, 0xffff }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct ecard_driver icside_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .probe = icside_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .remove = icside_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .shutdown = icside_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .id_table = icside_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = "icside",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int __init icside_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return ecard_register_driver(&icside_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static void __exit icside_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ecard_remove_driver(&icside_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MODULE_DESCRIPTION("ICS IDE driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) module_init(icside_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) module_exit(icside_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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