^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Portions Copyright (C) 2001 Sun Microsystems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Portions Copyright (C) 2003 Red Hat Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Thanks to HighPoint Technologies for their assistance, and hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * donation of an ABit BP6 mainboard, processor, and memory acellerated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * development and support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * HighPoint has its own drivers (open source except for the RAID part)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * available from http://www.highpoint-tech.com/USA_new/service_support.htm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This may be useful to anyone wanting to work on this driver, however do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * trust them too much since the code tends to become less and less meaningful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * as the time passes... :-/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Note that final HPT370 support was done by force extraction of GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - add function for getting/setting power status of drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - the HPT370's state machine can get confused. reset it before each dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * xfer to prevent that from happening.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * - reset state engine whenever we get an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - check for busmaster state at end of dma.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - use new highpoint timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - detect bus speed using highpoint register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - use pll if we don't have a clock table. added a 66MHz table that's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * just 2x the 33MHz table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - removed turnaround. NOTE: we never want to switch between pll and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * pci clocks as the chip can glitch in those cases. the highpoint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * approved workaround slows everything down too much to be useful. in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * addition, we would have to serialize access to each chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Adrian Sun <a.sun@sun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * add drive timings for 66MHz PCI bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * fix ATA Cable signal detection, fix incorrect /proc info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * add /proc display for per-drive PIO/DMA/UDMA mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * per-channel ATA-33/66 Cable detect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Duncan Laurie <void@sun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * fixup /proc output for multiple controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Tim Hockin <thockin@sun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * On hpt366:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Reset the hpt366 on error, reset on dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Fix disabling Fast Interrupt hpt366.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Mike Waychison <crlf@sun.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Added support for 372N clocking and clock switching. The 372N needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * different clocks on read/write. This requires overloading rw_disk and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * keeping me sane.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Alan Cox <alan@lxorguk.ukuu.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * - fix the clock turnaround code: it was writing to the wrong ports when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * called for the secondary channel, caching the current clock mode per-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * channel caused the cached register value to get out of sync with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * actual one, the channels weren't serialized, the turnaround shouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * be done on 66 MHz PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * does not allow for this speed anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * their primary channel is kind of virtual, it isn't tied to any pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * - fix/remove bad/unused timing tables and use one set of tables for the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * HPT37x chip family; save space by introducing the separate transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * table in which the mode lookup is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * read it only from the function 0 of HPT374 chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * they tamper with its fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * since they may tamper with its fields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * - prefix the driver startup messages with the real chip name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * - claim the extra 240 bytes of I/O space for all chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * - optimize the UltraDMA filtering and the drive list lookup code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * - use pci_get_slot() to get to the function 1 of HPT36x/374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * - cache offset of the channel's misc. control registers (MCRs) being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * throughout the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * - only touch the relevant MCR when detecting the cable type on HPT374's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * function 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * - rename all the register related variables consistently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * - move all the interrupt twiddling code from the speedproc handlers into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * init_hwif_hpt366(), also grouping all the DMA related code together there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * when setting an UltraDMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * the best possible one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * - clean up DMA timeout handling for HPT370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * - switch to using the enumeration type to differ between the numerous chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * variants, matching PCI device/revision ID with the chip type early, at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * init_setup stage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * stop duplicating it for each channel by storing the pointer in the pci_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * structure: first, at the init_setup stage, point it to a static "template"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * with only the chip type and its specific base DPLL frequency, the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * UltraDMA mode, and the chip settings table pointer filled, then, at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * init_chipset stage, allocate per-chip instance and fill it with the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * of the necessary information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * switch to calculating PCI clock frequency based on the chip's base DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * anything newer than HPT370/A (except HPT374 that is not capable of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * mode according to the manual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * unify HPT36x/37x timing setup code and the speedproc handlers by joining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * the register setting lists into the table indexed by the clock selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - set the correct hwif->ultra_mask for each individual chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * - stop resetting HPT370's state machine before each DMA transfer as that has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * caused more harm than good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRV_NAME "hpt366"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* various tuning parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #undef HPT_RESET_STATE_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #undef HPT_DELAY_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const char *bad_ata100_5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "IBM-DTLA-307075",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "IBM-DTLA-307060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "IBM-DTLA-307045",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "IBM-DTLA-307030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "IBM-DTLA-307020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "IBM-DTLA-307015",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "IBM-DTLA-305040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "IBM-DTLA-305030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) "IBM-DTLA-305020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "IC35L010AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "IC35L020AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "IC35L030AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "IC35L040AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "IC35L060AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char *bad_ata66_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "IBM-DTLA-307075",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "IBM-DTLA-307060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "IBM-DTLA-307045",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "IBM-DTLA-307030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "IBM-DTLA-307020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "IBM-DTLA-307015",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "IBM-DTLA-305040",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "IBM-DTLA-305030",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "IBM-DTLA-305020",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "IC35L010AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "IC35L020AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "IC35L030AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "IC35L040AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "IC35L060AVER07-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "MAXTOR STM3320620A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const char *bad_ata66_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "WDC AC310200R",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const char *bad_ata33[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "Maxtor 90510D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static u8 xfer_speeds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) XFER_UDMA_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) XFER_UDMA_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) XFER_UDMA_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) XFER_UDMA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) XFER_UDMA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) XFER_UDMA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) XFER_UDMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) XFER_MW_DMA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) XFER_MW_DMA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) XFER_MW_DMA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) XFER_PIO_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) XFER_PIO_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) XFER_PIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) XFER_PIO_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) XFER_PIO_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Key for bus clock timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 36x 37x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * bits bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * cycles = value + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * MW DMA xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * task file register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * 28 28 UDMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * 29 29 DMA enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * 30 30 PIO MST enable. If set, the chip is in bus master mode during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * PIO xfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * 31 31 FIFO enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static u32 forty_base_hpt36x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* XFER_UDMA_6 */ 0x900fd943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* XFER_UDMA_5 */ 0x900fd943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* XFER_UDMA_4 */ 0x900fd943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* XFER_UDMA_3 */ 0x900ad943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* XFER_UDMA_2 */ 0x900bd943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* XFER_UDMA_1 */ 0x9008d943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* XFER_UDMA_0 */ 0x9008d943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* XFER_MW_DMA_2 */ 0xa008d943,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* XFER_MW_DMA_1 */ 0xa010d955,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* XFER_MW_DMA_0 */ 0xa010d9fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* XFER_PIO_4 */ 0xc008d963,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* XFER_PIO_3 */ 0xc010d974,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* XFER_PIO_2 */ 0xc010d997,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* XFER_PIO_1 */ 0xc010d9c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* XFER_PIO_0 */ 0xc018d9d9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u32 thirty_three_base_hpt36x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* XFER_UDMA_6 */ 0x90c9a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* XFER_UDMA_5 */ 0x90c9a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* XFER_UDMA_4 */ 0x90c9a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* XFER_UDMA_3 */ 0x90cfa731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* XFER_UDMA_2 */ 0x90caa731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* XFER_UDMA_1 */ 0x90cba731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* XFER_UDMA_0 */ 0x90c8a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* XFER_MW_DMA_2 */ 0xa0c8a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* XFER_MW_DMA_0 */ 0xa0c8a797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* XFER_PIO_4 */ 0xc0c8a731,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* XFER_PIO_3 */ 0xc0c8a742,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* XFER_PIO_2 */ 0xc0d0a753,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static u32 twenty_five_base_hpt36x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* XFER_UDMA_6 */ 0x90c98521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* XFER_UDMA_5 */ 0x90c98521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* XFER_UDMA_4 */ 0x90c98521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* XFER_UDMA_3 */ 0x90cf8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* XFER_UDMA_2 */ 0x90cf8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* XFER_UDMA_1 */ 0x90cb8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* XFER_UDMA_0 */ 0x90cb8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* XFER_MW_DMA_2 */ 0xa0ca8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* XFER_MW_DMA_1 */ 0xa0ca8532,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* XFER_MW_DMA_0 */ 0xa0ca8575,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* XFER_PIO_4 */ 0xc0ca8521,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* XFER_PIO_3 */ 0xc0ca8532,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* XFER_PIO_2 */ 0xc0ca8542,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* XFER_PIO_1 */ 0xc0d08572,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* XFER_PIO_0 */ 0xc0d08585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * The following are the new timing tables with PIO mode data/taskfile transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * overclocking fixed...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* This table is taken from the HPT370 data manual rev. 1.02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static u32 thirty_three_base_hpt37x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* XFER_UDMA_5 */ 0x16455031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* XFER_UDMA_4 */ 0x16455031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* XFER_UDMA_3 */ 0x166d5031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* XFER_UDMA_2 */ 0x16495031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* XFER_UDMA_1 */ 0x164d5033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* XFER_UDMA_0 */ 0x16515097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* XFER_MW_DMA_2 */ 0x26515031,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* XFER_MW_DMA_1 */ 0x26515033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* XFER_MW_DMA_0 */ 0x26515097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* XFER_PIO_4 */ 0x06515021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* XFER_PIO_3 */ 0x06515022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* XFER_PIO_2 */ 0x06515033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* XFER_PIO_1 */ 0x06915065,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* XFER_PIO_0 */ 0x06d1508a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static u32 fifty_base_hpt37x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* XFER_UDMA_6 */ 0x1a861842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* XFER_UDMA_5 */ 0x1a861842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* XFER_UDMA_4 */ 0x1aae1842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* XFER_UDMA_3 */ 0x1a8e1842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* XFER_UDMA_2 */ 0x1a0e1842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* XFER_UDMA_1 */ 0x1a161854,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* XFER_UDMA_0 */ 0x1a1a18ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* XFER_MW_DMA_2 */ 0x2a821842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* XFER_MW_DMA_1 */ 0x2a821854,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* XFER_MW_DMA_0 */ 0x2a8218ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* XFER_PIO_4 */ 0x0a821842,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* XFER_PIO_3 */ 0x0a821843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* XFER_PIO_2 */ 0x0a821855,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* XFER_PIO_1 */ 0x0ac218a8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* XFER_PIO_0 */ 0x0b02190c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static u32 sixty_six_base_hpt37x[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* XFER_UDMA_6 */ 0x1c86fe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* XFER_UDMA_4 */ 0x1c8afe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* XFER_UDMA_3 */ 0x1c8efe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* XFER_UDMA_2 */ 0x1c92fe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* XFER_UDMA_1 */ 0x1c9afe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* XFER_UDMA_0 */ 0x1c82fe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* XFER_MW_DMA_2 */ 0x2c82fe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* XFER_MW_DMA_1 */ 0x2c82fe66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* XFER_MW_DMA_0 */ 0x2c82ff2e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* XFER_PIO_4 */ 0x0c82fe62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* XFER_PIO_3 */ 0x0c82fe84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* XFER_PIO_2 */ 0x0c82fea6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* XFER_PIO_1 */ 0x0d02ff26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* XFER_PIO_0 */ 0x0d42ff7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define HPT371_ALLOW_ATA133_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define HPT302_ALLOW_ATA133_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define HPT372_ALLOW_ATA133_6 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define HPT370_ALLOW_ATA100_5 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define HPT366_ALLOW_ATA66_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define HPT366_ALLOW_ATA66_3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Supported ATA clock frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) enum ata_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ATA_CLOCK_25MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ATA_CLOCK_33MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ATA_CLOCK_40MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ATA_CLOCK_50MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ATA_CLOCK_66MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) NUM_ATA_CLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct hpt_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u32 pio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 *clock_table[NUM_ATA_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Hold all the HighPoint chip information in one place.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct hpt_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) char *chip_name; /* Chip name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 chip_type; /* Chip type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 udma_mask; /* Allowed UltraDMA modes mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 dpll_clk; /* DPLL clock in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 pci_clk; /* PCI clock in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct hpt_timings *timings; /* Chipset timing data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 clock; /* ATA clock selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Supported HighPoint chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) HPT36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) HPT370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) HPT370A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) HPT374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) HPT372,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) HPT372A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) HPT302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) HPT371,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) HPT372N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) HPT302N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) HPT371N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct hpt_timings hpt36x_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .pio_mask = 0xc1f8ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .dma_mask = 0x303800ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .ultra_mask = 0x30070000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .clock_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) [ATA_CLOCK_50MHZ] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) [ATA_CLOCK_66MHZ] = NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct hpt_timings hpt37x_timings = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .pio_mask = 0xcfc3ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .dma_mask = 0x31c001ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .ultra_mask = 0x303c0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .clock_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [ATA_CLOCK_25MHZ] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [ATA_CLOCK_40MHZ] = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct hpt_info hpt36x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .chip_name = "HPT36x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .chip_type = HPT36x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .dpll_clk = 0, /* no DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .timings = &hpt36x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct hpt_info hpt370 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .chip_name = "HPT370",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .chip_type = HPT370,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .dpll_clk = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct hpt_info hpt370a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .chip_name = "HPT370A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .chip_type = HPT370A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .dpll_clk = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct hpt_info hpt374 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .chip_name = "HPT374",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .chip_type = HPT374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .udma_mask = ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .dpll_clk = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct hpt_info hpt372 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .chip_name = "HPT372",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .chip_type = HPT372,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .dpll_clk = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct hpt_info hpt372a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .chip_name = "HPT372A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .chip_type = HPT372A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .dpll_clk = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct hpt_info hpt302 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .chip_name = "HPT302",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .chip_type = HPT302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .dpll_clk = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct hpt_info hpt371 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .chip_name = "HPT371",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .chip_type = HPT371,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .dpll_clk = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct hpt_info hpt372n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .chip_name = "HPT372N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .chip_type = HPT372N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .dpll_clk = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct hpt_info hpt302n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .chip_name = "HPT302N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .chip_type = HPT302N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .dpll_clk = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct hpt_info hpt371n = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .chip_name = "HPT371N",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .chip_type = HPT371N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .dpll_clk = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .timings = &hpt37x_timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static bool check_in_drive_list(ide_drive_t *drive, const char **list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static struct hpt_info *hpt3xx_get_info(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ide_host *host = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct hpt_info *info = (struct hpt_info *)host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return dev == host->dev[1] ? info + 1 : info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * The Marvell bridge chips used on the HighPoint SATA cards do not seem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static u8 hpt3xx_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 mask = hwif->ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) switch (info->chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case HPT36x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!HPT366_ALLOW_ATA66_4 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) check_in_drive_list(drive, bad_ata66_4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mask = ATA_UDMA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!HPT366_ALLOW_ATA66_3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) check_in_drive_list(drive, bad_ata66_3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mask = ATA_UDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case HPT370:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!HPT370_ALLOW_ATA100_5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) check_in_drive_list(drive, bad_ata100_5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mask = ATA_UDMA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case HPT370A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (!HPT370_ALLOW_ATA100_5 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) check_in_drive_list(drive, bad_ata100_5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ATA_UDMA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case HPT372 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case HPT372A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case HPT372N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case HPT374 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ata_id_is_sata(drive->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mask &= ~0x0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) switch (info->chip_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case HPT372 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case HPT372A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case HPT372N:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case HPT374 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ata_id_is_sata(drive->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static u32 get_speed_setting(u8 speed, struct hpt_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * Lookup the transfer mode table to get the index into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * the timing table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (xfer_speeds[i] == speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return info->timings->clock_table[info->clock][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct hpt_timings *t = info->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u8 itr_addr = 0x40 + (drive->dn * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 old_itr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 new_itr = get_speed_setting(speed, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (speed < XFER_UDMA_0 ? t->dma_mask :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) t->ultra_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pci_read_config_dword(dev, itr_addr, &old_itr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * to avoid problems handling I/O errors later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) new_itr &= ~0xc0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pci_write_config_dword(dev, itr_addr, new_itr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) drive->dma_mode = drive->pio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) hpt3xx_set_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (info->chip_type >= HPT370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u8 scr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (((scr1 & 0x10) >> 4) != mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) scr1 |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) scr1 &= ~0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pci_write_config_byte(dev, 0x5a, scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) disable_irq(hwif->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) enable_irq(hwif->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * This is specific to the HPT366 UDMA chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * by HighPoint|Triones Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static void hpt366_dma_lost_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) pci_read_config_byte(dev, 0x52, &mcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) drive->name, __func__, mcr1, mcr3, scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (scr1 & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ide_dma_lost_irq(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void hpt370_clear_engine(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pci_write_config_byte(dev, hwif->select_data, 0x37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void hpt370_irq_timeout(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u16 bfifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 dma_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* get DMA command mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* stop DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) hpt370_clear_engine(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void hpt370_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #ifdef HPT_RESET_STATE_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) hpt370_clear_engine(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int hpt370_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (dma_stat & ATA_DMA_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* wait a little */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (dma_stat & ATA_DMA_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) hpt370_irq_timeout(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* returns 1 if DMA IRQ issued, 0 otherwise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int hpt374_dma_test_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u16 bfifo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u8 dma_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (bfifo & 0x1FF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* return 1 if INTR asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (dma_stat & ATA_DMA_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int hpt374_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u8 mcr = 0, mcr_addr = hwif->select_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pci_read_config_byte(dev, 0x6a, &bwsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pci_read_config_byte(dev, mcr_addr, &mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (bwsr & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * hpt3xxn_set_clock - perform clock switching dance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @hwif: hwif to switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * @mode: clocking mode (0x21 for write, 0x23 otherwise)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned long base = hwif->extra_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u8 scr2 = inb(base + 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if ((scr2 & 0x7f) == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Tristate the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) outb(0x80, base + 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) outb(0x80, base + 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Switch clock and reset channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) outb(mode, base + 0x6b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) outb(0xc0, base + 0x69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Reset the state machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * NOTE: avoid accidentally enabling the disabled channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) outb(inb(base + 0x60) | 0x32, base + 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) outb(inb(base + 0x64) | 0x32, base + 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* Complete reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) outb(0x00, base + 0x69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Reconnect channels to bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) outb(0x00, base + 0x63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) outb(0x00, base + 0x67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * hpt3xxn_rw_disk - prepare for I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * @drive: drive for command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * @rq: block request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * This is called when a disk I/O is issued to HPT3xxN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * We need it because of the clock switching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * hpt37x_calibrate_dpll - calibrate the DPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * Perform a calibration cycle on the DPLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Returns 1 if this succeeds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 dpll = (f_high << 16) | f_low | 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 scr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pci_write_config_dword(dev, 0x5c, dpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Wait for oscillator ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) for(i = 0; i < 0x5000; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pci_read_config_byte(dev, 0x5b, &scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (scr2 & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* See if it stays ready (we'll just bail out if it's not yet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) for(i = 0; i < 0x1000; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pci_read_config_byte(dev, 0x5b, &scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* DPLL destabilized? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if(!(scr2 & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Turn off tuning, we have the DPLL set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) pci_read_config_dword (dev, 0x5c, &dpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u8 chip_type = info->chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u8 new_mcr, old_mcr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * Disable the "fast interrupt" prediction. Don't hold off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * on interrupts. (== 0x01 despite what the docs say)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (chip_type >= HPT374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) new_mcr = old_mcr & ~0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) else if (chip_type >= HPT370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) new_mcr = old_mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) new_mcr &= ~0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #ifdef HPT_DELAY_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) new_mcr &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) new_mcr |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } else /* HPT366 and HPT368 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) new_mcr = old_mcr & ~0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (new_mcr != old_mcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int init_chipset_hpt366(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned long io_base = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct hpt_info *info = hpt3xx_get_info(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) const char *name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u8 chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) enum ata_clock clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) chip_type = info->chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * First, try to estimate the PCI clock frequency...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (chip_type >= HPT370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u8 scr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u16 f_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Interrupt force enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (scr1 & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * HighPoint does this for HPT372A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * NOTE: This register is only writeable via I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (chip_type == HPT372A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) outb(0x0e, io_base + 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * Default to PCI clock. Make sure MA15/16 are set to output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * to prevent drives having problems with 40-pin cables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pci_write_config_byte(dev, 0x5b, 0x23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * We'll have to read f_CNT value in order to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * the PCI clock frequency according to the following ratio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * f_CNT = Fpci * 192 / Fdpll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * First try reading the register in which the HighPoint BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * saves f_CNT value before reprogramming the DPLL from its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * default setting (which differs for the various chips).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * NOTE: This register is only accessible via I/O space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * HPT374 BIOS only saves it for the function 0, so we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * always read it from there -- no need to check the result of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * pci_get_slot() for the function 0 as the whole device has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * been already "pinned" (via function 1) in init_setup_hpt374()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct pci_dev *dev1 = pci_get_slot(dev->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev->devfn - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned long io_base = pci_resource_start(dev1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) temp = inl(io_base + 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pci_dev_put(dev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) temp = inl(io_base + 0x90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * In case the signature check fails, we'll have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * resort to reading the f_CNT register itself in hopes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * that nobody has touched the DPLL yet...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if ((temp & 0xFFFFF000) != 0xABCDE000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) printk(KERN_WARNING "%s %s: no clock data saved by "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "BIOS\n", name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Calculate the average value of f_CNT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) for (temp = i = 0; i < 128; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pci_read_config_word(dev, 0x78, &f_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) temp += f_cnt & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) f_cnt = temp / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) f_cnt = temp & 0x1ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dpll_clk = info->dpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pci_clk = (f_cnt * dpll_clk) / 192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Clamp PCI clock to bands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (pci_clk < 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pci_clk = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) else if(pci_clk < 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pci_clk = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) else if(pci_clk < 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) pci_clk = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pci_clk = 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "assuming %d MHz PCI\n", name, pci_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dpll_clk, f_cnt, pci_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) u32 itr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) pci_read_config_dword(dev, 0x40, &itr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* Detect PCI clock by looking at cmd_high_time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) switch ((itr1 >> 8) & 0x0f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case 0x09:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pci_clk = 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case 0x05:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) pci_clk = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) case 0x07:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) pci_clk = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Let's assume we'll use PCI clock for the ATA clock... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) switch (pci_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) case 25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) clock = ATA_CLOCK_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case 33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clock = ATA_CLOCK_33MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case 40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) clock = ATA_CLOCK_40MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case 50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) clock = ATA_CLOCK_50MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case 66:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) clock = ATA_CLOCK_66MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Only try the DPLL if we don't have a table for the PCI clock that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * we are running at for HPT370/A, always use it for anything newer...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * We also don't like using the DPLL because this causes glitches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * on PRST-/SRST- when the state engine gets reset...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u16 f_low, delta = pci_clk < 50 ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) int adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * Select 66 MHz DPLL clock only if UltraATA/133 mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * supported/enabled, use 50 MHz DPLL clock otherwise...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (info->udma_mask == ATA_UDMA6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dpll_clk = 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) clock = ATA_CLOCK_66MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dpll_clk = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) clock = ATA_CLOCK_50MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (info->timings->clock_table[clock] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) printk(KERN_ERR "%s %s: unknown bus timing!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Select the DPLL clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pci_write_config_byte(dev, 0x5b, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Adjust the DPLL based upon PCI clock, enable it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * and wait for stabilization...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) f_low = (pci_clk * 48) / dpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) for (adjust = 0; adjust < 8; adjust++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * See if it'll settle at a fractionally different clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (adjust & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) f_low -= adjust >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) f_low += adjust >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (adjust == 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) name, pci_name(dev), dpll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* Mark the fact that we're not using the DPLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dpll_clk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) name, pci_name(dev), pci_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Store the clock frequencies. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) info->dpll_clk = dpll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) info->pci_clk = pci_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) info->clock = clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (chip_type >= HPT370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) u8 mcr1, mcr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * Reset the state engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * NOTE: Avoid accidentally enabling the disabled channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) pci_read_config_byte (dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pci_read_config_byte (dev, 0x54, &mcr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * the MISC. register to stretch the UltraDMA Tss timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * NOTE: This register is only writeable via I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) hpt3xx_disable_fast_irq(dev, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) hpt3xx_disable_fast_irq(dev, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u8 chip_type = info->chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * The HPT37x uses the CBLID pins as outputs for MA15/MA16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * address lines to access an external EEPROM. To read valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * cable detect state the pins must be enabled as inputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * HPT374 PCI function 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * - set bit 15 of reg 0x52 to enable TCBLID as input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * - set bit 15 of reg 0x56 to enable FCBLID as input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u8 mcr_addr = hwif->select_data + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u16 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) pci_read_config_word(dev, mcr_addr, &mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Debounce, then read cable ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pci_write_config_word(dev, mcr_addr, mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else if (chip_type >= HPT370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * HPT370/372 and 374 pcifn 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u8 scr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pci_read_config_byte(dev, 0x5b, &scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pci_write_config_byte(dev, 0x5b, scr2 & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Debounce, then read cable ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) pci_write_config_byte(dev, 0x5b, scr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pci_read_config_byte(dev, 0x5a, &scr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static void init_hwif_hpt366(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct hpt_info *info = hpt3xx_get_info(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) u8 chip_type = info->chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* Cache the channel's MISC. control registers' offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) hwif->select_data = hwif->channel ? 0x54 : 0x50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * HPT3xxN chips have some complications:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * - on 33 MHz PCI we must clock switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * - on 66 MHz PCI we must NOT use the PCI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * Clock is shared between the channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * so we'll have to serialize them... :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) hwif->rw_disk = &hpt3xxn_rw_disk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int init_dma_hpt366(ide_hwif_t *hwif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) unsigned long flags, base = ide_pci_dma_base(hwif, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) hwif->dma_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ide_pci_check_simplex(hwif, d) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (ide_pci_set_master(dev, d->name) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dma_old = inb(base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dma_new = dma_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (masterdma & 0x30) dma_new |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if ( slavedma & 0x30) dma_new |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (dma_new != dma_old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) outb(dma_new, base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) hwif->name, base, base + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) hwif->extra_base = base + (hwif->channel ? 8 : 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ide_allocate_dma_engine(hwif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (dev2->irq != dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* FIXME: we need a core pci_set_interrupt() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev2->irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) "fixed\n", pci_name(dev2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static void hpt371_init(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u8 mcr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) * HPT371 chips physically have only one channel, the secondary one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * but the primary channel registers do exist! Go figure...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * So, we manually disable the non-existing channel here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * (if the BIOS hasn't done this already).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (mcr1 & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u8 mcr1 = 0, pin1 = 0, pin2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * Now we'll have to force both channels enabled if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * at least one of them has been enabled by BIOS...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pci_read_config_byte(dev, 0x50, &mcr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (mcr1 & 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (pin1 != pin2 && dev->irq == dev2->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define IDE_HFLAGS_HPT3XX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) (IDE_HFLAG_NO_ATAPI_DMA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) IDE_HFLAG_OFF_BOARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static const struct ide_port_ops hpt3xx_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .set_pio_mode = hpt3xx_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .set_dma_mode = hpt3xx_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .maskproc = hpt3xx_maskproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .mdma_filter = hpt3xx_mdma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .udma_filter = hpt3xx_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .cable_detect = hpt3xx_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static const struct ide_dma_ops hpt37x_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .dma_start = ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .dma_end = hpt374_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .dma_test_irq = hpt374_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct ide_dma_ops hpt370_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .dma_start = hpt370_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .dma_end = hpt370_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .dma_test_irq = ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .dma_clear = hpt370_irq_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const struct ide_dma_ops hpt36x_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .dma_start = ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .dma_end = ide_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .dma_test_irq = ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .dma_lost_irq = hpt366_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const struct ide_port_info hpt366_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) { /* 0: HPT36x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .init_chipset = init_chipset_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .init_hwif = init_hwif_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .init_dma = init_dma_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * HPT36x chips have one channel per function and have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * both channel enable bits located differently and visible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * to both functions -- really stupid design decision... :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * Bit 4 is for the primary channel, bit 5 for the secondary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .port_ops = &hpt3xx_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .dma_ops = &hpt36x_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) { /* 1: HPT3xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .init_chipset = init_chipset_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .init_hwif = init_hwif_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .init_dma = init_dma_hpt366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .port_ops = &hpt3xx_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .dma_ops = &hpt37x_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .host_flags = IDE_HFLAGS_HPT3XX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * hpt366_init_one - called when an HPT366 is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * @dev: the hpt366 device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * @id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) const struct hpt_info *info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct hpt_info *dyn_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct pci_dev *dev2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u8 rev = dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (rev < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) info = &hpt36x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) switch (min_t(u8, rev, 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) case 3: info = &hpt370; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) case 4: info = &hpt370a; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) case 5: info = &hpt372; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) case 6: info = &hpt372n; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) info = (rev > 1) ? &hpt372n : &hpt372a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) info = (rev > 1) ? &hpt302n : &hpt302;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) hpt371_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) info = (rev > 1) ? &hpt371n : &hpt371;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) info = &hpt374;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) info = &hpt372n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) d = hpt366_chipsets[min_t(u8, idx, 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) d.udma_mask = info->udma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* fixup ->dma_ops for HPT370/HPT370A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (info == &hpt370 || info == &hpt370a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) d.dma_ops = &hpt370_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (info == &hpt36x || info == &hpt374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) dyn_info = kcalloc(dev2 ? 2 : 1, sizeof(*dyn_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (dyn_info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) printk(KERN_ERR "%s %s: out of memory!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) d.name, pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * Copy everything from a static "template" structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * to just allocated per-chip hpt_info structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) memcpy(dyn_info, info, sizeof(*dyn_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (dev2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) memcpy(dyn_info + 1, info, sizeof(*dyn_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (info == &hpt374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) hpt374_init(dev, dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (hpt36x_init(dev, dev2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) kfree(dyn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = ide_pci_init_one(dev, &d, dyn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) kfree(dyn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static void hpt366_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct ide_info *info = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static const struct pci_device_id hpt366_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static struct pci_driver hpt366_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .name = "HPT366_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .id_table = hpt366_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .probe = hpt366_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .remove = hpt366_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static int __init hpt366_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return ide_pci_register_driver(&hpt366_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static void __exit hpt366_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) pci_unregister_driver(&hpt366_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) module_init(hpt366_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) module_exit(hpt366_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) MODULE_AUTHOR("Andre Hedrick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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