^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * CYPRESS CY82C693 chipset IDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRV_NAME "cy82c693"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * NOTE: the value for busmaster timeout is tricky and I got it by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * trial and error! By using a to low value will cause DMA timeouts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * and drop IDE performance, and by using a to high value will cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * audio playback to scatter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * If you know a better value or how to calc it, please let me know.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* twice the value written in cy82c693ub datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BUSMASTER_TIMEOUT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * the value above was tested on my machine and it seems to work okay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* here are the offset definitions for the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CY82_IDE_CMDREG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CY82_IDE_ADDRSETUP 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CY82_IDE_MASTER_IOR 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CY82_IDE_MASTER_IOW 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CY82_IDE_SLAVE_IOR 0x4E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CY82_IDE_SLAVE_IOW 0x4F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CY82_IDE_MASTER_8BIT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CY82_IDE_SLAVE_8BIT 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CY82_INDEX_PORT 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CY82_DATA_PORT 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CY82_INDEX_CHANNEL0 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CY82_INDEX_CHANNEL1 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CY82_INDEX_TIMEOUT 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * set DMA mode a specific channel for CY82C693
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const u8 mode = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) data = (mode & 3) | (single << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) outb(index, CY82_INDEX_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) outb(data, CY82_DATA_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * note: below we set the value for Bus Master IDE TimeOut Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * I'm not absolutely sure what this does, but it solved my problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * with IDE DMA and sound, so I now can play sound and work with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * my IDE driver at the same time :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * If you know the correct (best) value for this register please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * let me know - ASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) data = BUSMASTER_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) outb(data, CY82_DATA_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const unsigned long T = 1000000 / bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int addrCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct ide_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 time_16, time_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* select primary or secondary channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (drive->dn > 1) { /* drive is on the secondary channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev = pci_get_slot(dev->bus, dev->devfn+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) printk(KERN_ERR "%s: tune_drive: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "Cannot find secondary interface!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) drive->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) time_16 = clamp_val(t.recover - 1, 0, 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (clamp_val(t.active - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) time_8 = clamp_val(t.act8b - 1, 0, 15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (clamp_val(t.rec8b - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* now let's write the clocks registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if ((drive->dn & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * set master drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * address setup control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * is 32 bit !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) addrCtrl &= (~0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) addrCtrl |= clamp_val(t.setup - 1, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* now let's set the remaining registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * set slave drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * address setup control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * is 32 bit !!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) addrCtrl &= (~0xF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* now let's set the remaining registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (drive->dn > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci_dev_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void init_iops_cy82c693(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static ide_hwif_t *primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (PCI_FUNC(dev->devfn) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) primary = hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) hwif->mate = primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) hwif->channel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct ide_port_ops cy82c693_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .set_pio_mode = cy82c693_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .set_dma_mode = cy82c693_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct ide_port_info cy82c693_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .init_iops = init_iops_cy82c693,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .port_ops = &cy82c693_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .host_flags = IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .swdma_mask = ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int cy82c693_init_one(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct pci_dev *dev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* CY82C693 is more than only a IDE controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) Function 1 is primary IDE channel, function 2 - secondary. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PCI_FUNC(dev->devfn) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void cy82c693_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct ide_host *host = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pci_dev_put(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct pci_device_id cy82c693_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct pci_driver cy82c693_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "Cypress_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .id_table = cy82c693_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .probe = cy82c693_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .remove = cy82c693_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int __init cy82c693_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ide_pci_register_driver(&cy82c693_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void __exit cy82c693_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pci_unregister_driver(&cy82c693_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) module_init(cy82c693_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) module_exit(cy82c693_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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