Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * CS5536 PATA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * (C) 2007 Martin K. Petersen <mkp@mkp.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) 2009 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Available from AMD web site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * The IDE timing registers for the CS5536 live in the Geode Machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Specific Register file and not PCI config space.  Most BIOSes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * virtualize the PCI registers so the chip looks like a standard IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * controller.  Unfortunately not all implementations get this right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * In particular some have problems with unaligned accesses to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * virtualized PCI registers.  This driver always does full dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * writes to work around the issue.  Also, in case of a bad BIOS this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * driver can be loaded with the "msr=1" parameter which forces using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * the Machine Specific Registers to configure the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DRV_NAME	"cs5536"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MSR_IDE_CFG		= 0x51300010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	PCI_IDE_CFG		= 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	CFG			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	DTC			= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	CAST			= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	ETC			= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	IDE_CFG_CHANEN		= (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	IDE_CFG_CABLE		= (1 << 17) | (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	IDE_D0_SHIFT		= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	IDE_D1_SHIFT		= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	IDE_DRV_MASK		= 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	IDE_CAST_D0_SHIFT	= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	IDE_CAST_D1_SHIFT	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	IDE_CAST_DRV_MASK	= 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	IDE_CAST_CMD_SHIFT	= 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	IDE_CAST_CMD_MASK	= 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	IDE_ETC_UDMA_MASK	= 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int use_msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (unlikely(use_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		rdmsr(MSR_IDE_CFG + reg, *val, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static int cs5536_write(struct pci_dev *pdev, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (unlikely(use_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		wrmsr(MSR_IDE_CFG + reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static void cs5536_program_dtc(ide_drive_t *drive, u8 tim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct pci_dev *pdev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u32 dtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	cs5536_read(pdev, DTC, &dtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	dtc &= ~(IDE_DRV_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	dtc |= tim << dshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	cs5536_write(pdev, DTC, dtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  *	cs5536_cable_detect	-	detect cable type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  *	@hwif: Port to detect on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *	Perform cable detection for ATA66 capable cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  *	Returns a cable type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static u8 cs5536_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	cs5536_read(pdev, CFG, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (cfg & IDE_CFG_CABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  *	cs5536_set_pio_mode		-	PIO timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	@hwif: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *	@drive: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void cs5536_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	static const u8 drv_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		0x98, 0x55, 0x32, 0x21, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	static const u8 addr_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		0x2, 0x1, 0x0, 0x0, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	static const u8 cmd_timings[5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		0x99, 0x92, 0x90, 0x22, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int cshift = (drive->dn & 1) ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u32 cast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8 cmd_pio = pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (pair)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		cmd_pio = min_t(u8, pio, pair->pio_mode - XFER_PIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	timings &= (IDE_DRV_MASK << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	timings |= drv_timings[pio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	ide_set_drivedata(drive, (void *)timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	cs5536_program_dtc(drive, drv_timings[pio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	cs5536_read(pdev, CAST, &cast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	cast &= ~(IDE_CAST_DRV_MASK << cshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	cast |= addr_timings[pio] << cshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	cast |= cmd_timings[cmd_pio] << IDE_CAST_CMD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	cs5536_write(pdev, CAST, cast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  *	cs5536_set_dma_mode		-	DMA timing setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	@hwif: ATA port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	@drive: ATA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void cs5536_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	static const u8 udma_timings[6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	static const u8 mwdma_timings[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		0x67, 0x21, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int dshift = (drive->dn & 1) ? IDE_D1_SHIFT : IDE_D0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 etc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	const u8 mode = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	cs5536_read(pdev, ETC, &etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (mode >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		etc &= ~(IDE_DRV_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	} else { /* MWDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		etc &= ~(IDE_ETC_UDMA_MASK << dshift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		timings &= IDE_DRV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		timings |= mwdma_timings[mode - XFER_MW_DMA_0] << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		ide_set_drivedata(drive, (void *)timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	cs5536_write(pdev, ETC, etc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void cs5536_dma_start(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (drive->current_speed < XFER_UDMA_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	    (timings >> 8) != (timings & IDE_DRV_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		cs5536_program_dtc(drive, timings >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	ide_dma_start(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int cs5536_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int ret = ide_dma_end(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned long timings = (unsigned long)ide_get_drivedata(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (drive->current_speed < XFER_UDMA_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	    (timings >> 8) != (timings & IDE_DRV_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		cs5536_program_dtc(drive, timings & IDE_DRV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct ide_port_ops cs5536_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.set_pio_mode		= cs5536_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.set_dma_mode		= cs5536_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.cable_detect		= cs5536_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct ide_dma_ops cs5536_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.dma_host_set		= ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.dma_setup		= ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.dma_start		= cs5536_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.dma_end		= cs5536_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.dma_test_irq		= ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.dma_lost_irq		= ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.dma_sff_read_status	= ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct ide_port_info cs5536_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.port_ops	= &cs5536_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.dma_ops	= &cs5536_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.host_flags	= IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  *	cs5536_init_one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *	@dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *	@id: Entry in match table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (use_msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		printk(KERN_INFO DRV_NAME ": Using MSR regs instead of PCI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	cs5536_read(dev, CFG, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if ((cfg & IDE_CFG_CHANEN) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		printk(KERN_ERR DRV_NAME ": disabled by BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	return ide_pci_init_one(dev, &cs5536_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct pci_device_id cs5536_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct pci_driver cs5536_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.id_table	= cs5536_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.probe		= cs5536_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) module_pci_driver(cs5536_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_AUTHOR("Martin K. Petersen, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DEVICE_TABLE(pci, cs5536_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) module_param_named(msr, use_msr, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");