Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * - Reworked tuneproc, set_drive, misc mods to prep for mainline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * - Work was sponsored by CIS (M) Sdn Bhd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Ported to Kernel 2.6.11 on June 26, 2005 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   Alexander Kiausch <alex.kiausch@t-online.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Originally developed by AMD for 2.4/2.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Development of this chipset driver was funded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * by the nice folks at National Semiconductor/AMD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  CS5535 documentation available from AMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DRV_NAME "cs5535"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MSR_ATAC_BASE		0x51300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ATAC_RESET		(MSR_ATAC_BASE+0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define ATAC_BM0_CMD_PRIM	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define ATAC_BM0_STS_PRIM	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define ATAC_BM0_PRD		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CS5535_CABLE_DETECT	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Format I PIO settings. We separate out cmd and data for safer timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static unsigned int cs5535_pio_cmd_timings[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static unsigned int cs5535_pio_dta_timings[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static unsigned int cs5535_mwdma_timings[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static unsigned int cs5535_udma_timings[5] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* Macros to check if the register is the reset value -  reset value is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)    invalid timing and indicates the register has not been set previously */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /****
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	cs5535_set_speed         -     Configure the chipset to the new speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	@drive: Drive to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *	@speed: desired speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	cs5535_set_speed() configures the chipset to a new speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u32 reg = 0, dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u8 unit = drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Set the PIO timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (speed < XFER_SW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		u8 cmd, pioa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		cmd = pioa = speed - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			u8 piob = pair->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			if (piob < cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				cmd = piob;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Write the speed of the current drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			cs5535_pio_dta_timings[pioa];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		/* And if nessesary - change the speed of the other drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			cs5535_pio_cmd_timings[cmd]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			reg &= 0x0000FFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			reg |= cs5535_pio_cmd_timings[cmd] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		/* Set bit 31 of the DMA register for PIO format 1 timings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 					reg | 0x80000000UL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		reg &= 0x80000000UL;  /* Preserve the PIO format bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *	cs5535_set_dma_mode	-	set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *	@hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  *	Programs the chipset for DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	cs5535_set_speed(drive, drive->dma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  *	cs5535_set_pio_mode	-	set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  *	@hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  *	A callback from the upper layers for PIO-only tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	cs5535_set_speed(drive, drive->pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static u8 cs5535_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* if a 80 wire cable was detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct ide_port_ops cs5535_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.set_pio_mode		= cs5535_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.set_dma_mode		= cs5535_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.cable_detect		= cs5535_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct ide_port_info cs5535_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.port_ops	= &cs5535_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.udma_mask	= ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct pci_device_id cs5535_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct pci_driver cs5535_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.name		= "CS5535_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.id_table	= cs5535_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.probe		= cs5535_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int __init cs5535_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return ide_pci_register_driver(&cs5535_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __exit cs5535_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	pci_unregister_driver(&cs5535_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) module_init(cs5535_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) module_exit(cs5535_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_AUTHOR("AMD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_LICENSE("GPL");