^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Development of this chipset driver was funded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * by the nice folks at National Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * CS5530 documentation available from National Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRV_NAME "cs5530"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Here are the standard PIO mode 0-4 timings for each "format".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Format-0 uses fast data reg timings, with slower command reg timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Format-1 uses fast timings for all registers, but won't work with all drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned int cs5530_pio_timings[2][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * cs5530_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Handles setting of PIO mode for the chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * The init_hwif_cs5530() routine guarantees that all drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * will have valid default PIO timings set up before we get here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void cs5530_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long basereg = CS5530_BASEREG(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int format = (inl(basereg + 4) >> 31) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * cs5530_udma_filter - UDMA filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * cs5530_udma_filter() does UDMA mask filtering for the given drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * taking into the consideration capabilities of the mate device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * The CS5530 specifies that two drives sharing a cable cannot mix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * UDMA/MDMA. It has to be one or the other, for the pair, though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * different timings can still be chosen for each drive. We could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * set the appropriate timing bits on the fly, but that might be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * a bit confusing. So, for now we statically handle this requirement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * by looking at our mate drive to see what it is capable of, before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * choosing a mode for our own drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Note: This relies on the fact we never fail from UDMA to MWDMA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * but instead drop to PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static u8 cs5530_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ide_drive_t *mate = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 *mateid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 mask = hwif->ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (mate == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mateid = mate->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) (mateid[ATA_ID_UDMA_MODES] & 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (mateid[ATA_ID_MWDMA_MODES] & 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static void cs5530_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long basereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int reg, timings = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) switch (drive->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case XFER_UDMA_0: timings = 0x00921250; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case XFER_UDMA_1: timings = 0x00911140; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case XFER_UDMA_2: timings = 0x00911030; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case XFER_MW_DMA_0: timings = 0x00077771; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case XFER_MW_DMA_1: timings = 0x00012121; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) case XFER_MW_DMA_2: timings = 0x00002020; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) basereg = CS5530_BASEREG(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg = inl(basereg + 4); /* get drive0 config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) timings |= reg & 0x80000000; /* preserve PIO format bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) outl(timings, basereg + 4); /* write drive0 config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (timings & 0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg |= 0x00100000; /* enable UDMA timings for both drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg &= ~0x00100000; /* disable UDMA timings for both drives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) outl(reg, basereg + 4); /* write drive0 config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) outl(timings, basereg + 12); /* write drive1 config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * init_chipset_5530 - set up 5530 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Initialize the cs5530 bridge for reliable IDE DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int init_chipset_cs5530(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (pci_resource_start(dev, 4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) master_0 = pci_dev_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cs5530_0 = pci_dev_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!master_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!cs5530_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pci_set_master(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_try_set_mwi(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Set PCI CacheLineSize to 16-bytes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Disable trapping of UDMA register accesses (Win98 hack):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pci_write_config_word(cs5530_0, 0xd0, 0x5006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * The other settings are what is necessary to get the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * into a sane state for IDE DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_write_config_byte(master_0, 0x40, 0x1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Set max PCI burst size (16-bytes seems to work best):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * all others: clear bit-1 at 0x41, and do:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 128bytes: OR 0x00 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 256bytes: OR 0x04 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 512bytes: OR 0x08 at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 1024bytes: OR 0x0c at 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_write_config_byte(master_0, 0x41, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * These settings are necessary to get the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * into a sane state for IDE DMA operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pci_write_config_byte(master_0, 0x42, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pci_write_config_byte(master_0, 0x43, 0xc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pci_dev_put(master_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pci_dev_put(cs5530_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * init_hwif_cs5530 - initialise an IDE channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @hwif: IDE to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * This gets invoked by the IDE driver once for each channel. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * performs channel-specific pre-initialization before drive probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void init_hwif_cs5530 (ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long basereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 d0_timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) basereg = CS5530_BASEREG(hwif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) d0_timings = inl(basereg + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (CS5530_BAD_PIO(d0_timings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (CS5530_BAD_PIO(inl(basereg + 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct ide_port_ops cs5530_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .set_pio_mode = cs5530_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .set_dma_mode = cs5530_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .udma_filter = cs5530_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct ide_port_info cs5530_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .init_chipset = init_chipset_cs5530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .init_hwif = init_hwif_cs5530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .port_ops = &cs5530_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .host_flags = IDE_HFLAG_SERIALIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IDE_HFLAG_POST_SET_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .udma_mask = ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ide_pci_init_one(dev, &cs5530_chipset, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct pci_device_id cs5530_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct pci_driver cs5530_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "CS5530 IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .id_table = cs5530_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .probe = cs5530_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int __init cs5530_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return ide_pci_register_driver(&cs5530_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void __exit cs5530_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pci_unregister_driver(&cs5530_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_init(cs5530_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) module_exit(cs5530_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_AUTHOR("Mark Lord");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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