Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *           Due to massive hardware bugs, UltraDMA is only supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *           on the 646U2 and not on the 646U.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 1998		David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright (C) 2007-2010	Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Copyright (C) 2007,2009	MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DRV_NAME "cmd64x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * CMD64x specific registers definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CFR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define   CFR_INTR_CH0		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	CMDTIM		0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	ARTTIM0		0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	DRWTIM0		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ARTTIM1 	0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DRWTIM1		0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ARTTIM23	0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define   ARTTIM23_DIS_RA2	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define   ARTTIM23_DIS_RA3	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define   ARTTIM23_INTR_CH1	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DRWTIM2		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BRST		0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DRWTIM3		0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BMIDECR0	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MRDMODE		0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define   MRDMODE_INTR_CH0	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define   MRDMODE_INTR_CH1	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define UDIDETCR0	0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DTPR0		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define BMIDECR1	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BMIDECSR	0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define UDIDETCR1	0x7B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define DTPR1		0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void cmd64x_program_timings(ide_drive_t *drive, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	const unsigned long T = 1000000 / bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	static const u8 recovery_values[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct ide_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u8 arttim = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (drive->dn >= ARRAY_SIZE(drwtim_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	ide_timing_compute(drive, mode, &t, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * In case we've got too long recovery phase, try to lengthen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * the active phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	if (t.recover > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		t.active += t.recover - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		t.recover = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (t.active > 16)		/* shouldn't actually happen... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		t.active = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * Convert values to internal chipset representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	t.recover = recovery_values[t.recover];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	t.active &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Program the active/recovery counts into the DRWTIM register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	pci_write_config_byte(dev, drwtim_regs[drive->dn],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			      (t.active << 4) | t.recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * The primary channel has individual address setup timing registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * for each drive and the hardware selects the slowest timing itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * The secondary channel has one common register and we have to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * the slowest address setup timing ourselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (hwif->channel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			struct ide_timing tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			ide_timing_compute(pair, pair->pio_mode, &tp, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			if (pair->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				ide_timing_compute(pair, pair->dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 						&tp, T, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 				ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (t.setup > 5)		/* shouldn't actually happen... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		t.setup = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * Program the address setup clocks into the ARTTIM registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Avoid clearing the secondary channel's interrupt bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	(void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (hwif->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		arttim &= ~ARTTIM23_INTR_CH1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	arttim &= ~0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	arttim |= setup_values[t.setup];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * Attempts to set drive's PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void cmd64x_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * Filter out the prefetch control values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * to prevent PIO5 from being programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (pio == 8 || pio == 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	cmd64x_program_timings(drive, XFER_PIO_0 + pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void cmd64x_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8 unit			= drive->dn & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u8 regU = 0, pciU	= hwif->channel ? UDIDETCR1 : UDIDETCR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	const u8 speed		= drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	pci_read_config_byte(dev, pciU, &regU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	regU &= ~(unit ? 0xCA : 0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	switch(speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case XFER_UDMA_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		regU |= unit ? 0x0A : 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case XFER_UDMA_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		regU |= unit ? 0x4A : 0x15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case XFER_UDMA_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		regU |= unit ? 0x8A : 0x25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case XFER_UDMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		regU |= unit ? 0x42 : 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	case XFER_UDMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		regU |= unit ? 0x82 : 0x21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case XFER_UDMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		regU |= unit ? 0xC2 : 0x31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case XFER_MW_DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case XFER_MW_DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	case XFER_MW_DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		cmd64x_program_timings(drive, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pci_write_config_byte(dev, pciU, regU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void cmd648_clear_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	ide_hwif_t *hwif	= drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	unsigned long base	= pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u8  irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 						  MRDMODE_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u8  mrdmode		= inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	/* clear the interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	     base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void cmd64x_clear_irq(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	ide_hwif_t *hwif	= drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 						  CFR_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u8  irq_stat		= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* clear the interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	(void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int cmd648_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	unsigned long base	= pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	u8 irq_mask		= hwif->channel ? MRDMODE_INTR_CH1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 						  MRDMODE_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u8 mrdmode		= inb(base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		 hwif->name, mrdmode, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return (mrdmode & irq_mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int cmd64x_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int irq_reg		= hwif->channel ? ARTTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u8  irq_mask		= hwif->channel ? ARTTIM23_INTR_CH1 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 						  CFR_INTR_CH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u8  irq_stat		= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	(void) pci_read_config_byte(dev, irq_reg, &irq_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		 hwif->name, irq_stat, irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return (irq_stat & irq_mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * event order for DMA transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int cmd646_1_dma_end(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ide_hwif_t *hwif = drive->hwif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u8 dma_stat = 0, dma_cmd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/* get DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* read DMA command state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* stop DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* clear the INTR & ERROR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* verify good DMA status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return (dma_stat & 7) != 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int init_chipset_cmd64x(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	u8 mrdmode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* Set a good latency timer and cache line size value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	(void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* FIXME: pci_set_master() to ensure a good latency timer value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * Enable interrupts, select MEMORY READ LINE for reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * NOTE: although not mentioned in the PCI0646U specs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * bits 0-1 are write only and won't be read back as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * set or not -- PCI0646U2 specs clarify this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	(void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	mrdmode &= ~0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	(void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct pci_dev  *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	u8 bmidecsr = 0, mask	= hwif->channel ? 0x02 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	switch (dev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	case PCI_DEVICE_ID_CMD_648:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	case PCI_DEVICE_ID_CMD_649:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)  		pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct ide_port_ops cmd64x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.set_pio_mode		= cmd64x_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.set_dma_mode		= cmd64x_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.clear_irq		= cmd64x_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.test_irq		= cmd64x_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.cable_detect		= cmd64x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct ide_port_ops cmd648_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.set_pio_mode		= cmd64x_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.set_dma_mode		= cmd64x_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.clear_irq		= cmd648_clear_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.test_irq		= cmd648_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.cable_detect		= cmd64x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct ide_dma_ops cmd646_rev1_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.dma_host_set		= ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.dma_setup		= ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.dma_start		= ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.dma_end		= cmd646_1_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.dma_test_irq		= ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.dma_lost_irq		= ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.dma_sff_read_status	= ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct ide_port_info cmd64x_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{	/* 0: CMD643 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.init_chipset	= init_chipset_cmd64x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.enablebits	= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.port_ops	= &cmd64x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.host_flags	= IDE_HFLAG_CLEAR_SIMPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 				  IDE_HFLAG_ABUSE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				  IDE_HFLAG_SERIALIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.pio_mask	= ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.udma_mask	= 0x00, /* no udma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	{	/* 1: CMD646 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.init_chipset	= init_chipset_cmd64x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.port_ops	= &cmd648_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				  IDE_HFLAG_SERIALIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.pio_mask	= ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		.udma_mask	= ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	{	/* 2: CMD648 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		.init_chipset	= init_chipset_cmd64x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.port_ops	= &cmd648_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		.pio_mask	= ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		.udma_mask	= ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	{	/* 3: CMD649 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.init_chipset	= init_chipset_cmd64x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.enablebits	= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		.port_ops	= &cmd648_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.host_flags	= IDE_HFLAG_ABUSE_PREFETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.pio_mask	= ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	d = cmd64x_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (idx == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		 * UltraDMA only supported on PCI646U and PCI646U2, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		 * Actually, although the CMD tech support people won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		 * tell me the details, the 0x03 revision cannot support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		 * UDMA correctly without hardware modifications, and even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		 * then it only works with Quantum disks due to some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		 * hold time assumptions in the 646U part which are fixed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		 * in the 646U2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		if (dev->revision < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			d.udma_mask = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			 * The original PCI0646 didn't have the primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			 * channel enable bit, it appeared starting with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			 * PCI0646U (i.e. revision ID 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			if (dev->revision < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 				d.enablebits[0].reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				d.port_ops = &cmd64x_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 				if (dev->revision == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 					d.dma_ops = &cmd646_rev1_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct pci_device_id cmd64x_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct pci_driver cmd64x_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	.name		= "CMD64x_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	.id_table	= cmd64x_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.probe		= cmd64x_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int __init cmd64x_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	return ide_pci_register_driver(&cmd64x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void __exit cmd64x_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	pci_unregister_driver(&cmd64x_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) module_init(cmd64x_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) module_exit(cmd64x_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_LICENSE("GPL");