^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * mlord@pobox.com (Mark Lord)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * See linux/MAINTAINERS for address of current maintainer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file provides support for the advanced features and bugs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * These chips are basically fucked by design, and getting this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * to work on every motherboard design that uses this screwed chip seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * bloody well impossible. However, we're still trying.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Version 0.97 worked for everybody.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * User feedback is essential. Many thanks to the beta test team:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * liug@mama.indstate.edu, and others.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Version 0.01 Initial version, hacked out of ide.c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * and #include'd rather than compiled separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * This will get cleaned up in a subsequent release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Version 0.02 Fixes for vlb initialization code, enable prefetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * for versions 'B' and 'C' of chip by default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * some code cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Version 0.03 Added reset of secondary interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * and black list for devices which are not compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * with prefetch mode. Separate function for setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * prefetch is added, possibly it will be called some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * day from ioctl processing code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Version 0.04 Now configs/compiles separate from ide.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Version 0.05 Major rewrite of interface timing code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Added new function cmd640_set_mode to set PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * from ioctl call. New drives added to black list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Version 0.06 More code cleanup. Prefetch is enabled only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * detected hard drives, not included in prefetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * black list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Version 0.07 Changed to more conservative drive tuning policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Unknown drives, which report PIO < 4 are set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * (reported_PIO - 1) if it is supported, or to PIO0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * List of known drives extended by info provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * CMD at their ftp site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Version 0.08 Added autotune/noautotune support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Version 0.09 Try to be smarter about 2nd port enabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Version 0.10 Be nice and don't reset 2nd port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Version 0.11 Try to handle more weird situations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Version 0.12 Lots of bug fixes from Laszlo Peter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * irq unmasking disabled for reliability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * try to be even smarter about the second port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * tidy up source code formatting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Version 0.13 permit irq unmasking again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Version 0.90 massive code cleanup, some bugs fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * defaults all drives to PIO mode0, prefetch off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * autotune is OFF by default, with compile time flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * (requires hdparm-3.1 or newer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Version 0.91 first release to linux-kernel list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Version 0.92 move initial reg dump to separate callable function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * change "readahead" to "prefetch" to avoid confusion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Version 0.95 respect original BIOS timings unless autotuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * tons of code cleanup and rearrangement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * added CONFIG_BLK_DEV_CMD640_ENHANCED option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * prevent use of unmask when prefetch is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Version 0.96 prevent use of io_32bit when prefetch is off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Version 0.97 fix VLB secondary interface for sjd@slip.net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * other minor tune-ups: 0.96 was very good.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Version 0.98 ignore PCI version when disabled by BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Version 0.99 display setup/active/recovery clocks with PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * ("fast" is necessary for 32bit I/O in some systems)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Version 1.02 fix bug that resulted in slow "setup times"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * (patch courtesy of Zoltan Hidvegi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMD640_PREFETCH_MASKS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*#define CMD640_DUMP_REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DRV_NAME "cmd640"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static bool cmd640_vlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * CMD640 specific registers definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DID 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCMD_ENA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PSTTS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REVID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PROGIF 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SUBCL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BASCL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BaseA0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BaseA1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BaseA2 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BaseA3 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INTLINE 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INPINE 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CFR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CFR_DEVREV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CFR_IDE01INTR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CFR_DEVID 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CFR_AT_VESA_078h 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CFR_DSA1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CFR_DSA0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CNTRL 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CNTRL_DIS_RA0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CNTRL_DIS_RA1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CNTRL_ENA_2ND 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMDTIM 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ARTTIM0 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DRWTIM0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ARTTIM1 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DRWTIM1 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ARTTIM23 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ARTTIM23_DIS_RA2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ARTTIM23_DIS_RA3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ARTTIM23_IDE23INTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DRWTIM23 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BRST 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Registers and masks for easy access by drive index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Current cmd640 timing values for each drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * The defaults for each are the slowest possible timings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static DEFINE_SPINLOCK(cmd640_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Interface to access cmd640x registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static unsigned int cmd640_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void (*__put_cmd640_reg)(u16 reg, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static u8 (*__get_cmd640_reg)(u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * This is read from the CFR reg, and is used in several places.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned int cmd640_chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * The CMD640x chip does not support DWORD config write cycles, but some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * of the BIOSes use them to implement the config services.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Therefore, we must use direct IO instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* PCI method 1 access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void put_cmd640_reg_pci1(u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) outb_p(val, (reg & 3) | 0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static u8 get_cmd640_reg_pci1(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return inb_p((reg & 3) | 0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* PCI method 2 access (from CMD datasheet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void put_cmd640_reg_pci2(u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) outb_p(0x10, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) outb_p(val, cmd640_key + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) outb_p(0, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static u8 get_cmd640_reg_pci2(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) outb_p(0x10, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) b = inb_p(cmd640_key + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) outb_p(0, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* VLB access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void put_cmd640_reg_vlb(u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) outb_p(reg, cmd640_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) outb_p(val, cmd640_key + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static u8 get_cmd640_reg_vlb(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) outb_p(reg, cmd640_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return inb_p(cmd640_key + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static u8 get_cmd640_reg(u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) b = __get_cmd640_reg(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void put_cmd640_reg(u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __put_cmd640_reg(reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int __init match_pci_cmd640_device(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (get_cmd640_reg(i) != ven_dev[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) printk("ide: cmd640 on PCI disabled by BIOS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Probe for CMD640x -- pci method 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int __init probe_for_cmd640_pci1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __get_cmd640_reg = get_cmd640_reg_pci1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __put_cmd640_reg = put_cmd640_reg_pci1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) for (cmd640_key = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cmd640_key <= 0x8000f800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cmd640_key += 0x800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (match_pci_cmd640_device())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Probe for CMD640x -- pci method 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int __init probe_for_cmd640_pci2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __get_cmd640_reg = get_cmd640_reg_pci2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __put_cmd640_reg = put_cmd640_reg_pci2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (match_pci_cmd640_device())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Probe for CMD640x -- vlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int __init probe_for_cmd640_vlb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __get_cmd640_reg = get_cmd640_reg_vlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __put_cmd640_reg = put_cmd640_reg_vlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cmd640_key = 0x178;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) b = get_cmd640_reg(CFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cmd640_key = 0x78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) b = get_cmd640_reg(CFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Returns 1 if an IDE interface/drive exists at 0x170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Returns 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int __init secondary_port_responding(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) outb_p(0x0a, 0x176); /* select drive0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((inb_p(0x176) & 0x1f) != 0x0a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) outb_p(0x1a, 0x176); /* select drive1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if ((inb_p(0x176) & 0x1f) != 0x1a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0; /* nothing responded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #ifdef CMD640_DUMP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Dump out all cmd640 registers. May be called from ide.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void cmd640_dump_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Dump current state of chip registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) printk("ide: cmd640 internal register dump:");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (; reg <= 0x59; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!(reg & 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) printk("\n%04x:", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) printk(" %02x", get_cmd640_reg(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void __set_prefetch_mode(ide_drive_t *drive, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (mode) { /* want prefetch on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #if CMD640_PREFETCH_MASKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) drive->dev_flags &= ~IDE_DFLAG_UNMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) drive->dev_flags &= ~IDE_DFLAG_NO_IO_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) drive->dev_flags &= ~IDE_DFLAG_NO_UNMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) drive->dev_flags |= IDE_DFLAG_NO_IO_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) drive->io_32bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Check whether prefetch is on for a drive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * and initialize the unmask flags for safe operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 b = get_cmd640_reg(prefetch_regs[index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) __set_prefetch_mode(drive, (b & prefetch_masks[index]) ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * Sets prefetch mode for a drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int reg = prefetch_regs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) b = __get_cmd640_reg(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __set_prefetch_mode(drive, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) b &= ~prefetch_masks[index]; /* enable prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) b |= prefetch_masks[index]; /* disable prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) __put_cmd640_reg(reg, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Dump out current drive clocks settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void display_clocks(unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 active_count, recovery_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) active_count = active_counts[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (active_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ++active_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) recovery_count = recovery_counts[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (active_count > 3 && recovery_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ++recovery_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (cmd640_chip_version > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) recovery_count += 1; /* cmd640b uses (count + 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Pack active and recovery counts into single byte representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * used by controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static inline u8 pack_nibbles(u8 upper, u8 lower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ((upper & 0x0f) << 4) | (lower & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * This routine writes the prepared setup/active/recovery counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * for a drive into the cmd640 chipset registers to active them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void program_drive_counts(ide_drive_t *drive, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 setup_count = setup_counts[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 active_count = active_counts[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 recovery_count = recovery_counts[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Set up address setup count and drive read/write timing registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Primary interface has individual count/timing registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * each drive. Secondary interface has one common set of registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * so we merge the timings, using the slowest value for each timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (index > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ide_drive_t *peer = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned int mate = index ^ 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (setup_count < setup_counts[mate])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) setup_count = setup_counts[mate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (active_count < active_counts[mate])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) active_count = active_counts[mate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (recovery_count < recovery_counts[mate])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) recovery_count = recovery_counts[mate];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Convert setup_count to internal chipset representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch (setup_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case 4: setup_count = 0x00; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case 3: setup_count = 0x80; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case 2: setup_count = 0x40; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) default: setup_count = 0xc0; /* case 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Now that everything is ready, program the new timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Program the address_setup clocks into ARTTIM reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * and then the active/recovery counts into the DRWTIM reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * (this converts counts of 16 into counts of zero -- okay).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __put_cmd640_reg(arttim_regs[index], setup_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * Set a specific pio_mode for a drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u8 pio_mode, unsigned int cycle_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ide_timing *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int setup_time, active_time, recovery_time, clock_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (cmd640_vlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (pio_mode > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pio_mode = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) t = ide_timing_find_mode(XFER_PIO_0 + pio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) setup_time = t->setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) active_time = t->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) recovery_time = cycle_time - (setup_time + active_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) clock_time = 1000 / bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) cycle_count = DIV_ROUND_UP(cycle_time, clock_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) setup_count = DIV_ROUND_UP(setup_time, clock_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) active_count = DIV_ROUND_UP(active_time, clock_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (active_count < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) active_count = 2; /* minimum allowed by cmd640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) recovery_count = DIV_ROUND_UP(recovery_time, clock_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) recovery_count2 = cycle_count - (setup_count + active_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (recovery_count2 > recovery_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) recovery_count = recovery_count2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (recovery_count < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) recovery_count = 2; /* minimum allowed by cmd640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (recovery_count > 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) active_count += recovery_count - 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) recovery_count = 17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (active_count > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) active_count = 16; /* maximum allowed by cmd640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (cmd640_chip_version > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) recovery_count -= 1; /* cmd640b uses (count + 1)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (recovery_count > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) recovery_count = 16; /* maximum allowed by cmd640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) setup_counts[index] = setup_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) active_counts[index] = active_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) recovery_counts[index] = recovery_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * In a perfect world, we might set the drive pio mode here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * (using WIN_SETFEATURE) before continuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * But we do not, because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * 1) this is the wrong place to do it (proper is do_special() in ide.c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * 2) in practice this is rarely, if ever, necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) program_drive_counts(drive, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static void cmd640_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned int index = 0, cycle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) switch (pio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case 6: /* set fast-devsel off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case 7: /* set fast-devsel on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) b = get_cmd640_reg(CNTRL) & ~0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (pio & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) b |= 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) put_cmd640_reg(CNTRL, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) printk("%s: %sabled cmd640 fast host timing (devsel)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) drive->name, (pio & 1) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case 8: /* set prefetch off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case 9: /* set prefetch on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) set_prefetch_mode(drive, index, pio & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) printk("%s: %sabled cmd640 prefetch\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) drive->name, (pio & 1) ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) cycle_time = ide_pio_cycle_time(drive, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) cmd640_set_mode(drive, index, pio, cycle_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) printk("%s: selected cmd640 PIO mode%d (%dns)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) drive->name, pio, cycle_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) display_clocks(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void __init cmd640_init_dev(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Reset timing to the slowest speed and turn off prefetch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * This way, the drive identify code has a better chance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) setup_counts[i] = 4; /* max possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) active_counts[i] = 16; /* max possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) recovery_counts[i] = 16; /* max possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) program_drive_counts(drive, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) set_prefetch_mode(drive, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch cleared\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Set the drive unmask flags to match the prefetch setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) check_prefetch(drive, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch(%s) preserved\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) i, (drive->dev_flags & IDE_DFLAG_NO_IO_32BIT) ? "off" : "on");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int cmd640_test_irq(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int irq_reg = hwif->channel ? ARTTIM23 : CFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u8 irq_mask = hwif->channel ? ARTTIM23_IDE23INTR :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) CFR_IDE01INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u8 irq_stat = get_cmd640_reg(irq_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return (irq_stat & irq_mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct ide_port_ops cmd640_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .init_dev = cmd640_init_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .set_pio_mode = cmd640_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .test_irq = cmd640_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static int pci_conf1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) outb(0x01, 0xCFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) tmp = inl(0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) outl(0x80000000, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (inl(0xCF8) == 0x80000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) outl(tmp, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) outl(tmp, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int pci_conf2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_lock_irqsave(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) outb(0x00, 0xCFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) outb(0x00, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) outb(0x00, 0xCFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_unlock_irqrestore(&cmd640_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct ide_port_info cmd640_port_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .chipset = ide_cmd640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .host_flags = IDE_HFLAG_SERIALIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) IDE_HFLAG_NO_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) IDE_HFLAG_ABUSE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) IDE_HFLAG_ABUSE_FAST_DEVSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .port_ops = &cmd640_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pio_mask = ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int __init cmd640x_init_one(unsigned long base, unsigned long ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (!request_region(base, 8, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) DRV_NAME, base, base + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!request_region(ctl, 1, DRV_NAME)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) DRV_NAME, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) release_region(base, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * Probe for a cmd640 chipset, and initialize it if found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int __init cmd640x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int second_port_cmd640 = 0, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) const char *bus_type, *port2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u8 b, cfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct ide_hw hw[2], *hws[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (cmd640_vlb && probe_for_cmd640_vlb()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bus_type = "VLB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) cmd640_vlb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Find out what kind of PCI probing is supported otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) Justin Gibbs will sulk.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (pci_conf1() && probe_for_cmd640_pci1())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) bus_type = "PCI (type1)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) else if (pci_conf2() && probe_for_cmd640_pci2())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) bus_type = "PCI (type2)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Undocumented magic (there is no 0x5b reg in specs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) put_cmd640_reg(0x5b, 0xbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (get_cmd640_reg(0x5b) != 0xbd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) put_cmd640_reg(0x5b, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #ifdef CMD640_DUMP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) cmd640_dump_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Documented magic begins here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cfr = get_cmd640_reg(CFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) cmd640_chip_version = cfr & CFR_DEVREV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (cmd640_chip_version == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rc = cmd640x_init_one(0x1f0, 0x3f6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) rc = cmd640x_init_one(0x170, 0x376);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) release_region(0x3f6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) release_region(0x1f0, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) memset(&hw, 0, sizeof(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) hw[0].irq = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ide_std_init_ports(&hw[1], 0x170, 0x376);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) hw[1].irq = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Initialize data for primary port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) hws[0] = &hw[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * Ensure compatibility by always using the slowest timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * for access to the drive's command register block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * and reset the prefetch burstsize to default (512 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * Maybe we need a way to NOT do these on *some* systems?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) put_cmd640_reg(CMDTIM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) put_cmd640_reg(BRST, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) b = get_cmd640_reg(CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * Try to enable the secondary interface, if not already enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (secondary_port_responding()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if ((b & CNTRL_ENA_2ND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) second_port_cmd640 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) port2 = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) } else if (cmd640_vlb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) second_port_cmd640 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) port2 = "alive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) port2 = "not cmd640";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (secondary_port_responding()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) second_port_cmd640 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) port2 = "enabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) put_cmd640_reg(CNTRL, b); /* restore original setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) port2 = "not responding";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * Initialize data for secondary cmd640 port, if enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (second_port_cmd640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) hws[1] = &hw[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) second_port_cmd640 ? "" : "not ", port2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #ifdef CMD640_DUMP_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) cmd640_dump_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ide_host_add(&cmd640_port_info, hws, second_port_cmd640 ? 2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) module_param_named(probe_vlb, cmd640_vlb, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) module_init(cmd640x_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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