Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DRV_NAME "atiixp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ATIIXP_IDE_PIO_TIMING		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ATIIXP_IDE_MDMA_TIMING		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define ATIIXP_IDE_PIO_CONTROL		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define ATIIXP_IDE_PIO_MODE		0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ATIIXP_IDE_UDMA_CONTROL		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ATIIXP_IDE_UDMA_MODE		0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) struct atiixp_ide_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u8 command_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 recover_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct atiixp_ide_timing pio_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{ 0x05, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{ 0x04, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{ 0x03, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{ 0x02, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{ 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct atiixp_ide_timing mdma_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{ 0x07, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{ 0x02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{ 0x02, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static DEFINE_SPINLOCK(atiixp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *	atiixp_set_pio_mode	-	set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *	@hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *	Set the interface PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static void atiixp_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int timing_shift = (drive->dn ^ 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 pio_timing_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u16 pio_mode_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	spin_lock_irqsave(&atiixp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pio_mode_data &= ~(0x07 << (drive->dn * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	pio_mode_data |= (pio << (drive->dn * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	pio_timing_data &= ~(0xff << timing_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 (pio_timing[pio].command_width << (timing_shift + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	spin_unlock_irqrestore(&atiixp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *	atiixp_set_dma_mode	-	set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *	@hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  *	@drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *	Set a ATIIXP host controller to the desired DMA mode.  This involves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *	programming the right timing data into the PCI configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static void atiixp_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int timing_shift = (drive->dn ^ 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 tmp32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u16 tmp16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u16 udma_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	spin_lock_irqsave(&atiixp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (speed >= XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		tmp16 &= ~(0x07 << (drive->dn * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		tmp16 |= ((speed & 0x07) << (drive->dn * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		udma_ctl |= (1 << drive->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	} else if (speed >= XFER_MW_DMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		u8 i = speed & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		tmp32 &= ~(0xff << timing_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			 (mdma_timing[i].command_width << (timing_shift + 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		udma_ctl &= ~(1 << drive->dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spin_unlock_irqrestore(&atiixp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static u8 atiixp_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 udma_mode = 0, ch = hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct ide_port_ops atiixp_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.set_pio_mode		= atiixp_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.set_dma_mode		= atiixp_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.cable_detect		= atiixp_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct ide_port_info atiixp_pci_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{	/* 0: IXP200/300/400/700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.enablebits	= {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.port_ops	= &atiixp_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{	/* 1: IXP600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.enablebits	= {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.port_ops	= &atiixp_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.host_flags	= IDE_HFLAG_SINGLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  *	atiixp_init_one	-	called when a ATIIXP is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  *	@dev: the atiixp device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  *	@id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  *	Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *	finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct pci_device_id atiixp_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct pci_driver atiixp_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.name		= "ATIIXP_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.id_table	= atiixp_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.probe		= atiixp_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int __init atiixp_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return ide_pci_register_driver(&atiixp_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void __exit atiixp_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	pci_unregister_driver(&atiixp_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) module_init(atiixp_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) module_exit(atiixp_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MODULE_AUTHOR("HUI YU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_LICENSE("GPL");