Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * IDE driver for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2000-2002 Vojtech Pavlik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on the work of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *      Andre Hedrick
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DRV_NAME "amd74xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	AMD_IDE_CONFIG		= 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	AMD_CABLE_DETECT	= 0x42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	AMD_DRIVE_TIMING	= 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	AMD_8BIT_TIMING		= 0x4e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	AMD_ADDRESS_SETUP	= 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	AMD_UDMA_TIMING		= 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static unsigned int amd_80w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static unsigned int amd_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static inline u8 amd_offset(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * amd_set_speed() writes timing values to the chipset registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			  struct ide_timing *timing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u8 t = 0, offset = amd_offset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	switch (udma_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	default: return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (timing->udma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * amd_set_drive() computes timing values and configures the chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * to a desired transfer mode.  It also can be called by upper layers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ide_drive_t *peer = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct ide_timing t, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int T, UT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 udma_mask = hwif->ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	T = 1000000000 / amd_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	ide_timing_compute(drive, speed, &t, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (peer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		ide_timing_compute(peer, peer->pio_mode, &p, T, UT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	amd_set_speed(dev, drive->dn, udma_mask, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	drive->dma_mode = drive->pio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	amd_set_drive(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void amd7409_cable_detect(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* no host side cable detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	amd_80w = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void amd7411_cable_detect(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 u = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 t = 0, offset = amd_offset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	for (i = 24; i >= 0; i -= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				"cable bits correctly. Enabling workaround.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			amd_80w |= (1 << (1 - (i >> 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * The initialization callback.  Initialize drive independent registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int init_chipset_amd74xx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	u8 t = 0, offset = amd_offset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * Check 80-wire cable presence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (dev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	    dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		; /* no UDMA > 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	else if (dev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		amd7409_cable_detect(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		amd7411_cable_detect(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * Take care of prefetch & postwrite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * Check for broken FIFO support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (dev->vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	    dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		t &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		t |= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static u8 amd_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if ((amd_80w >> hwif->channel) & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return ATA_CBL_PATA40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct ide_port_ops amd_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.set_pio_mode		= amd_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.set_dma_mode		= amd_set_drive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.cable_detect		= amd_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IDE_HFLAGS_AMD \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	(IDE_HFLAG_PIO_NO_BLACKLIST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 IDE_HFLAG_POST_SET_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 IDE_HFLAG_IO_32BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 IDE_HFLAG_UNMASK_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DECLARE_AMD_DEV(swdma, udma)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.name		= DRV_NAME,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.init_chipset	= init_chipset_amd74xx,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.enablebits	= {{0x40,0x02,0x02}, {0x40,0x01,0x01}},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.port_ops	= &amd_port_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.host_flags	= IDE_HFLAGS_AMD,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.pio_mask	= ATA_PIO5,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.swdma_mask	= swdma,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.mwdma_mask	= ATA_MWDMA2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.udma_mask	= udma,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DECLARE_NV_DEV(udma)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.name		= DRV_NAME,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.init_chipset	= init_chipset_amd74xx,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.enablebits	= {{0x50,0x02,0x02}, {0x50,0x01,0x01}},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.port_ops	= &amd_port_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.host_flags	= IDE_HFLAGS_AMD,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.pio_mask	= ATA_PIO5,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.swdma_mask	= ATA_SWDMA2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.mwdma_mask	= ATA_MWDMA2,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.udma_mask	= udma,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct ide_port_info amd74xx_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* 0: AMD7401 */	DECLARE_AMD_DEV(0x00, ATA_UDMA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* 1: AMD7409 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* 2: AMD7411/7441 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* 3: AMD8111 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* 4: NFORCE */		DECLARE_NV_DEV(ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/* 5: >= NFORCE2 */	DECLARE_NV_DEV(ATA_UDMA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* 6: AMD5536 */	DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	d = amd74xx_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (idx == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		if (dev->revision <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			d.swdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	} else if (idx == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		    dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			d.udma_mask = ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * It seems that on some nVidia controllers using AltStatus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * register can be unreliable so default to Status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * if the device is in Compatibility Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	    ide_pci_is_in_compatibility_mode(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	printk(KERN_INFO "%s %s: UDMA%s controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	* Determine the system bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	switch (amd_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case 33000: amd_clock = 33333; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case 37000: amd_clock = 37500; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case 41000: amd_clock = 41666; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (amd_clock < 20000 || amd_clock > 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		printk(KERN_WARNING "%s: User given PCI clock speed impossible"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				    " (%d), using 33 MHz instead.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				    d.name, amd_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		amd_clock = 33333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct pci_device_id amd74xx_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_COBRA_7401),		 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7409),		 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_VIPER_7411),		 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_OPUS_7441),		 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_8111_IDE),		 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),	 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_BLK_DEV_IDE_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ PCI_VDEVICE(NVIDIA,	PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE),	 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ PCI_VDEVICE(AMD,	PCI_DEVICE_ID_AMD_CS5536_IDE),		 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static struct pci_driver amd74xx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.name		= "AMD_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.id_table	= amd74xx_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.probe		= amd74xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.remove		= ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int __init amd74xx_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return ide_pci_register_driver(&amd74xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void __exit amd74xx_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	pci_unregister_driver(&amd74xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) module_init(amd74xx_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_exit(amd74xx_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("AMD PCI IDE driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL");