^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 1998-2000 Michel Aubry, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * May be copied or modified under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2002 Alan Cox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (U)DMA capable version of ali 1533/1543(C), 1535(D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 9/7/99 --Parts from the above author are included and need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * converted into standard interface, once I finish the thought.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Recent changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Don't use LBA48 mode on ALi <= 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Don't poke 0x79 with a non ALi northbridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Allow UDMA6 on revisions > 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Chipset documentation available under NDA only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DRV_NAME "alim15x3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * ALi devices are not plug in. Otherwise these static values would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * need to go. They ought to go away anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static u8 m5229_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u8 chip_is_1543c_e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct pci_dev *isa_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct pci_dev *pdev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int pio_fifo = 0x54 + hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int shift = 4 * (drive->dn & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pci_read_config_byte(pdev, pio_fifo, &fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) fifo &= ~(0x0F << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) fifo |= (on << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pci_write_config_byte(pdev, pio_fifo, fifo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct ide_timing *t, u8 ultra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int port = hwif->channel ? 0x5c : 0x58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int udmat = 0x56 + hwif->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 unit = drive->dn & 1, udma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int shift = 4 * unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Set up the UDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_read_config_byte(dev, udmat, &udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) udma &= ~(0x0F << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) udma |= ultra << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pci_write_config_byte(dev, udmat, udma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (t == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) t->setup = clamp_val(t->setup, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) t->act8b = clamp_val(t->act8b, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) t->active = clamp_val(t->active, 1, 8) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) t->recover = clamp_val(t->recover, 1, 16) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_write_config_byte(dev, port, t->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pci_write_config_byte(dev, port + unit + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (t->active << 4) | t->recover);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * ali_set_pio_mode - set host controller for PIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Program the controller for the given PIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned long T = 1000000 / bus_speed; /* PCI clock based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct ide_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ide_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ide_timing_merge(&p, &t, &t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) IDE_TIMING_SETUP | IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (pair->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ide_timing_compute(pair, pair->dma_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ide_timing_merge(&p, &t, &t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) IDE_TIMING_SETUP | IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * PIO mode => ATA FIFO on, ATAPI FIFO off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ali_program_timings(hwif, drive, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * ali_udma_filter - compute UDMA mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @drive: IDE device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Return available UDMA modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * The actual rules for the ALi are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * No UDMA on revisions <= 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Disk only for revisions < 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Not WDC drives on M1543C-E (?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u8 ali_udma_filter(ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (drive->media != ide_disk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (chip_is_1543c_e &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return drive->hwif->ultra_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * ali_set_dma_mode - set host controller for DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @hwif: port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @drive: drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Configure the hardware for the desired IDE transfer mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static u8 udma_timing[7] = { 0xC, 0xB, 0xA, 0x9, 0x8, 0xF, 0xD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ide_drive_t *pair = ide_get_pair_dev(drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long T = 1000000 / bus_speed; /* PCI clock based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 tmpbyte = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ide_timing t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (speed < XFER_UDMA_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ide_timing_compute(drive, drive->dma_mode, &t, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (pair) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ide_timing p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ide_timing_merge(&p, &t, &t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IDE_TIMING_SETUP | IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pair->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ide_timing_compute(pair, pair->dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &p, T, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ide_timing_merge(&p, &t, &t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IDE_TIMING_SETUP | IDE_TIMING_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ali_program_timings(hwif, drive, &t, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ali_program_timings(hwif, drive, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) udma_timing[speed - XFER_UDMA_0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (speed >= XFER_UDMA_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci_read_config_byte(dev, 0x4b, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tmpbyte |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pci_write_config_byte(dev, 0x4b, tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * ali_dma_check - DMA check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @drive: target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @cmd: command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Returns 1 if the DMA cannot be performed, zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int ali_dma_check(ide_drive_t *drive, struct ide_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (m5229_revision < 0xC2 && drive->media != ide_disk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (cmd->tf_flags & IDE_TFLAG_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 1; /* try PIO instead of DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * init_chipset_ali15x3 - Initialise an ALi IDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @dev: PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * This function initializes the ALI IDE controller and where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * appropriate also sets up the 1533 southbridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int init_chipset_ali15x3(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 tmpbyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) m5229_revision = dev->revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (m5229_revision < 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * revision 0x20 (1543-E, 1543-F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pci_read_config_byte(dev, 0x4b, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * clear bit 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (m5229_revision >= 0x20 && isa_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 1543C-B?, 1535, 1535D, 1553
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Note 1: not all "motherboard" support this detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Note 2: if no udma 66 device, the detection may "error".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * but in this case, we will not set the device to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * ultra 66, the detection result is not important
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * enable "Cable Detection", m5229, 0x4b, bit3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pci_read_config_byte(dev, 0x4b, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * We should only tune the 1533 enable if we are using an ALi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * North bridge. We might have no north found on some zany
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * box without a device at 0:0.0. The ALi bridge will be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * 0:0.0 so if we didn't find one we know what is cooking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (north && north->vendor != PCI_VENDOR_ID_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (m5229_revision < 0xC5 && isa_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * set south-bridge's enable bit, m1533, 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (m5229_revision == 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * 1543C-B0 (m1533, 0x79, bit 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } else if (m5229_revision >= 0xC3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * 1553/1535 (m1533, 0x79, bit 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * CD_ROM DMA on (m5229, 0x53, bit0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * Enable this bit even if we want to use PIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * PIO FIFO off (m5229, 0x53, bit1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * The hardware will use 0x54h and 0x55h to control PIO FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * (Not on later devices it seems)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 0x53 changes meaning on later revs - we must no touch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * bit 1 on them. Need to check if 0x20 is the right break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (m5229_revision >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pci_read_config_byte(dev, 0x53, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (m5229_revision <= 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tmpbyte = (tmpbyte & (~0x02)) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tmpbyte |= 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tmpbyte |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pci_write_config_byte(dev, 0x53, tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pci_dev_put(north);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) pci_dev_put(isa_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Cable special cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct dmi_system_id cable_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .ident = "HP Pavilion N5430",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .ident = "Toshiba Satellite S1800-814",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int ali_cable_override(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Fujitsu P2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (pdev->subsystem_vendor == 0x10CF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pdev->subsystem_device == 0x10AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Mitac 8317 (Winbook-A) and relatives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (pdev->subsystem_vendor == 0x1071 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pdev->subsystem_device == 0x8317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Systems by DMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (dmi_check_system(cable_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * ali_cable_detect - cable detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @hwif: IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * This checks if the controller and the cable are capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * of UDMA66 transfers. It doesn't check the drives.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static u8 ali_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 cbl = ATA_CBL_PATA40, tmpbyte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (m5229_revision >= 0xC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * m5229 80-pin cable detection (from Host View)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * 0x4a bit0 is 0 => primary channel has 80-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * 0x4a bit1 is 0 => secondary channel has 80-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Certain laptops use short but suitable cables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * and don't implement the detect logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ali_cable_override(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) cbl = ATA_CBL_PATA40_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pci_read_config_byte(dev, 0x4a, &tmpbyte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if ((tmpbyte & (1 << hwif->channel)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cbl = ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return cbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifndef CONFIG_SPARC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @hwif: interface to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Obtain the IRQ tables for an ALi based IDE solution on the PC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * class platforms. This part of the code isn't applicable to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Sparc systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void init_hwif_ali15x3(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 ideic, inmir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 1, 11, 0, 12, 0, 14, 0, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (isa_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * read IDE interface control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_read_config_byte(isa_dev, 0x58, &ideic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* bit0, bit1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ideic = ideic & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* get IRQ for IDE Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((hwif->channel && ideic == 0x03) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) (!hwif->channel && !ideic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * get SIRQ1 routing table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pci_read_config_byte(isa_dev, 0x44, &inmir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) inmir = inmir & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) irq = irq_routing_table[inmir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else if (hwif->channel && !(ideic & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * get SIRQ2 routing table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pci_read_config_byte(isa_dev, 0x75, &inmir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) inmir = inmir & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) irq = irq_routing_table[inmir];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if(irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hwif->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define init_hwif_ali15x3 NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #endif /* CONFIG_SPARC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * init_dma_ali15x3 - set up DMA on ALi15x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * @hwif: IDE interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @d: IDE port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Set up the DMA functionality on the ALi 15x3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int init_dma_ali15x3(ide_hwif_t *hwif, const struct ide_port_info *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long base = ide_pci_dma_base(hwif, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) hwif->dma_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ide_pci_check_simplex(hwif, d) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ide_pci_set_master(dev, d->name) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!hwif->channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) outb(inb(base + 2) & 0x60, base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) hwif->name, base, base + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ide_allocate_dma_engine(hwif))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct ide_port_ops ali_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .set_pio_mode = ali_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .set_dma_mode = ali_set_dma_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .udma_filter = ali_udma_filter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .cable_detect = ali_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct ide_dma_ops ali_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .dma_host_set = ide_dma_host_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .dma_setup = ide_dma_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .dma_start = ide_dma_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .dma_end = ide_dma_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .dma_test_irq = ide_dma_test_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .dma_lost_irq = ide_dma_lost_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .dma_check = ali_dma_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .dma_timer_expiry = ide_dma_sff_timer_expiry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .dma_sff_read_status = ide_dma_sff_read_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct ide_port_info ali15x3_chipset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .init_chipset = init_chipset_ali15x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .init_hwif = init_hwif_ali15x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .init_dma = init_dma_ali15x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .port_ops = &ali_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .dma_ops = &sff_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .pio_mask = ATA_PIO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .swdma_mask = ATA_SWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .mwdma_mask = ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * alim15x3_init_one - set up an ALi15x3 IDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @dev: PCI device to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Perform the actual set up for an ALi15x3 that has been found by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * hot plug layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int alim15x3_init_one(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct ide_port_info d = ali15x3_chipset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u8 rev = dev->revision, idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (rev <= 0xC4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (rev >= 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (rev == 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (rev < 0xC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) d.udma_mask = ATA_UDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else if (rev == 0xC2 || rev == 0xC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) d.udma_mask = ATA_UDMA4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else if (rev == 0xC4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) d.udma_mask = ATA_UDMA5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) d.udma_mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) d.dma_ops = &ali_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) d.host_flags |= IDE_HFLAG_NO_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) d.mwdma_mask = d.swdma_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ide_pci_init_one(dev, &d, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const struct pci_device_id alim15x3_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static struct pci_driver alim15x3_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "ALI15x3_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .id_table = alim15x3_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .probe = alim15x3_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .remove = ide_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .suspend = ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .resume = ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int __init ali15x3_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ide_pci_register_driver(&alim15x3_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static void __exit ali15x3_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pci_unregister_driver(&alim15x3_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) module_init(ali15x3_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) module_exit(ali15x3_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox, Bartlomiej Zolnierkiewicz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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