^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 1996 Linus Torvalds & author (see below)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * ALI M14xx chipset EIDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Works for ALI M1439/1443/1445/1487/1489 chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Adapted from code developed by derekn@vw.ece.cmu.edu. -ml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Derek's notes follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * I think the code should be pretty understandable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * but I'll be happy to (try to) answer questions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The critical part is in the setupDrive function. The initRegisters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * function doesn't seem to be necessary, but the DOS driver does it, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * I threw it in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * I've only tested this on my system, which only has one disk. I posted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * it to comp.sys.linux.hardware, so maybe some other people will try it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Derek Noonburg (derekn@ece.cmu.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 95-sep-26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Update 96-jul-13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * I've since upgraded to two disks and a CD-ROM, with no trouble, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * I've also heard from several others who have used it successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This driver appears to work with both the 1443/1445 and the 1487/1489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * chipsets. I've added support for PIO mode 4 for the 1487. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * seems to work just fine on the 1443 also, although I'm not sure it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * advertised as supporting mode 4. (I've been running a WDC AC21200 in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * mode 4 for a while now with no trouble.) -Derek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/blkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRV_NAME "ali14xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* port addresses for auto-detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ALI_NUM_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const int ports[ALI_NUM_PORTS] __initconst =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { 0x074, 0x0f4, 0x034, 0x0e4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* register initialization data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) typedef struct { u8 reg, data; } RegInitializer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const RegInitializer initData[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {0x01, 0x0f}, {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {0x05, 0x00}, {0x06, 0x00}, {0x07, 0x2b}, {0x0a, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x00}, {0x28, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {0x29, 0x00}, {0x2a, 0x00}, {0x2f, 0x00}, {0x2b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {0x2c, 0x00}, {0x2d, 0x00}, {0x2e, 0x00}, {0x30, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0x31, 0x00}, {0x32, 0x00}, {0x33, 0x00}, {0x34, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0x35, 0x03}, {0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* timing parameter registers for each drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {0x03, 0x26, 0x04, 0x27}, /* drive 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {0x05, 0x28, 0x06, 0x29}, /* drive 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0x2b, 0x30, 0x2c, 0x31}, /* drive 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {0x2d, 0x32, 0x2e, 0x33}, /* drive 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int basePort; /* base port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int regPort; /* port for register number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int dataPort; /* port for register data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static u8 regOn; /* output to base port to access registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static u8 regOff; /* output to base port to close registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Read a controller register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline u8 inReg(u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) outb_p(reg, regPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return inb(dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Write a controller register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void outReg(u8 data, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) outb_p(reg, regPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) outb_p(data, dataPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static DEFINE_SPINLOCK(ali14xx_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Set PIO mode for the specified drive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * This function computes timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * and sets controller registers accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void ali14xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int driveNum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int time1, time2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 param1, param2, param3, param4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const u8 pio = drive->pio_mode - XFER_PIO_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* calculate timing, according to PIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) time1 = ide_pio_cycle_time(drive, pio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) time2 = t->active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) param3 = param1 = (time2 * bus_speed + 999) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) param4 = param2 = (time1 * bus_speed + 999) / 1000 - param1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (pio < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) param3 += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) param4 += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) printk(KERN_DEBUG "%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) drive->name, pio, time1, time2, param1, param2, param3, param4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* stuff timing parameters into controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) driveNum = (drive->hwif->index << 1) + (drive->dn & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_lock_irqsave(&ali14xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) outb_p(regOn, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) outReg(param1, regTab[driveNum].reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) outReg(param2, regTab[driveNum].reg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) outReg(param3, regTab[driveNum].reg3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) outReg(param4, regTab[driveNum].reg4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) outb_p(regOff, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_unlock_irqrestore(&ali14xx_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Auto-detect the IDE controller port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __init findPort(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < ALI_NUM_PORTS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) basePort = ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regOff = inb(basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (regOn = 0x30; regOn <= 0x33; ++regOn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) outb_p(regOn, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (inb(basePort) == regOn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regPort = basePort + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dataPort = basePort + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) t = inReg(0) & 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) outb_p(regOff, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (t != 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 1; /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) outb_p(regOff, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Initialize controller registers with default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int __init initRegisters(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const RegInitializer *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) outb_p(regOn, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (p = initData; p->reg != 0; ++p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) outReg(p->data, p->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) outb_p(0x01, regPort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) t = inb(regPort) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) outb_p(regOff, basePort);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct ide_port_ops ali14xx_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .set_pio_mode = ali14xx_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct ide_port_info ali14xx_port_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .chipset = ide_ali14xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .port_ops = &ali14xx_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .host_flags = IDE_HFLAG_NO_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pio_mask = ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init ali14xx_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) printk(KERN_DEBUG "ali14xx: base=0x%03x, regOn=0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) basePort, regOn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* initialize controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!initRegisters()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) printk(KERN_ERR "ali14xx: Chip initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ide_legacy_device_add(&ali14xx_port_info, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static bool probe_ali14xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_param_named(probe, probe_ali14xx, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MODULE_PARM_DESC(probe, "probe for ALI M14xx chipsets");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int __init ali14xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (probe_ali14xx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* auto-detect IDE controller port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (findPort()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ali14xx_probe())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) printk(KERN_ERR "ali14xx: not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) module_init(ali14xx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MODULE_AUTHOR("see local file");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_DESCRIPTION("support of ALI 14XX IDE chipsets");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags