Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/ide.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DRV_NAME "aec62xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct chipset_bus_clock_list_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	u8 xfer_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	u8 chipset_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u8 ultra_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{	XFER_UDMA_6,	0x31,	0x07	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	{	XFER_UDMA_5,	0x31,	0x06	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	{	XFER_UDMA_4,	0x31,	0x05	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	{	XFER_UDMA_3,	0x31,	0x04	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{	XFER_UDMA_2,	0x31,	0x03	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	{	XFER_UDMA_1,	0x31,	0x02	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{	XFER_UDMA_0,	0x31,	0x01	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{	XFER_MW_DMA_2,	0x31,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	{	XFER_MW_DMA_1,	0x31,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{	XFER_MW_DMA_0,	0x0a,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	{	XFER_PIO_4,	0x31,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	{	XFER_PIO_3,	0x33,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	{	XFER_PIO_2,	0x08,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{	XFER_PIO_1,	0x0a,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	{	XFER_PIO_0,	0x00,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	{	0,		0x00,	0x00	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{	XFER_UDMA_6,	0x41,	0x06	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{	XFER_UDMA_5,	0x41,	0x05	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{	XFER_UDMA_4,	0x41,	0x04	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{	XFER_UDMA_3,	0x41,	0x03	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{	XFER_UDMA_2,	0x41,	0x02	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{	XFER_UDMA_1,	0x41,	0x01	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	{	XFER_UDMA_0,	0x41,	0x01	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{	XFER_MW_DMA_2,	0x41,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{	XFER_MW_DMA_1,	0x42,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{	XFER_MW_DMA_0,	0x7a,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{	XFER_PIO_4,	0x41,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{	XFER_PIO_3,	0x43,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{	XFER_PIO_2,	0x78,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{	XFER_PIO_1,	0x7a,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{	XFER_PIO_0,	0x70,	0x00	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{	0,		0x00,	0x00	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * TO DO: active tuning and correction of cards without a bios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	for ( ; chipset_table->xfer_speed ; chipset_table++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		if (chipset_table->xfer_speed == speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			return chipset_table->chipset_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return chipset_table->chipset_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	for ( ; chipset_table->xfer_speed ; chipset_table++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		if (chipset_table->xfer_speed == speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			return chipset_table->ultra_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return chipset_table->ultra_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct ide_host *host	= pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u16 d_conf		= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u8 ultra = 0, ultra_conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	tmp0 = pci_bus_clock_list(speed, bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tmp1 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tmp2 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pci_read_config_byte(dev, 0x54, &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	pci_write_config_byte(dev, 0x54, tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct pci_dev *dev	= to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct ide_host *host	= pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8 unit			= drive->dn & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u8 tmp1 = 0, tmp2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	const u8 speed = drive->dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* high 4-bits: Active, low 4-bits: Recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	drive_conf = pci_bus_clock_list(speed, bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	drive->dma_mode = drive->pio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	hwif->port_ops->set_dma_mode(hwif, drive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int init_chipset_aec62xx(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* These are necessary to get AEC6280 Macintosh cards to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		u8 reg49h = 0, reg4ah = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		/* Clear reset and test bits.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		pci_read_config_byte(dev, 0x49, &reg49h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		/* Enable chip interrupt output.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		pci_read_config_byte(dev, 0x4a, &reg4ah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* Enable burst mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		pci_read_config_byte(dev, 0x4a, &reg4ah);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static u8 atp86x_cable_detect(ide_hwif_t *hwif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	struct pci_dev *dev = to_pci_dev(hwif->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	pci_read_config_byte(dev, 0x49, &ata66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct ide_port_ops atp850_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.set_pio_mode		= aec_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.set_dma_mode		= aec6210_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct ide_port_ops atp86x_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set_pio_mode		= aec_set_pio_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.set_dma_mode		= aec6260_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.cable_detect		= atp86x_cable_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct ide_port_info aec62xx_chipsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{	/* 0: AEC6210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.init_chipset	= init_chipset_aec62xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.port_ops	= &atp850_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.host_flags	= IDE_HFLAG_SERIALIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				  IDE_HFLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				  IDE_HFLAG_NO_DSC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.udma_mask	= ATA_UDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{	/* 1: AEC6260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.init_chipset	= init_chipset_aec62xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.port_ops	= &atp86x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.udma_mask	= ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{	/* 2: AEC6260R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.init_chipset	= init_chipset_aec62xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.port_ops	= &atp86x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				  IDE_HFLAG_NON_BOOTABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.udma_mask	= ATA_UDMA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	{	/* 3: AEC6280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.init_chipset	= init_chipset_aec62xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.port_ops	= &atp86x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{	/* 4: AEC6280R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.name		= DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.init_chipset	= init_chipset_aec62xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.port_ops	= &atp86x_port_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 				  IDE_HFLAG_OFF_BOARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.pio_mask	= ATA_PIO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.mwdma_mask	= ATA_MWDMA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.udma_mask	= ATA_UDMA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  *	aec62xx_init_one	-	called when a AEC is found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  *	@dev: the aec62xx device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  *	@id: the matching pci id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  *	Called when the PCI registration layer (or the IDE initialization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  *	finds a device matching our IDE device tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	const struct chipset_bus_clock_list_entry *bus_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct ide_port_info d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u8 idx = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (bus_speed <= 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		bus_clock = aec6xxx_33_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		bus_clock = aec6xxx_34_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	err = pci_enable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	d = aec62xx_chipsets[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (idx == 3 || idx == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		unsigned long dma_base = pci_resource_start(dev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (inb(dma_base + 2) & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 				"\n", pci_name(dev), (idx == 4) ? "R" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			d.udma_mask = ATA_UDMA6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void aec62xx_remove(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	ide_pci_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	pci_disable_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct pci_device_id aec62xx_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct pci_driver aec62xx_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.name		= "AEC62xx_IDE",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.id_table	= aec62xx_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.probe		= aec62xx_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.remove		= aec62xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.suspend	= ide_pci_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.resume		= ide_pci_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int __init aec62xx_ide_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return ide_pci_register_driver(&aec62xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void __exit aec62xx_ide_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	pci_unregister_driver(&aec62xx_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) module_init(aec62xx_ide_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) module_exit(aec62xx_ide_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_AUTHOR("Andre Hedrick");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MODULE_LICENSE("GPL");