^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Boris Brezillon <boris.brezillon@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i3c/master.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DEV_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DEV_ID_I3C_MASTER 0x5034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CONF_STATUS0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CONF_STATUS0_CMDR_DEPTH(x) (4 << (((x) & GENMASK(31, 29)) >> 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CONF_STATUS0_ECC_CHK BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CONF_STATUS0_INTEG_CHK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CONF_STATUS0_CSR_DAP_CHK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CONF_STATUS0_TRANS_TOUT_CHK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CONF_STATUS0_PROT_FAULTS_CHK BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CONF_STATUS0_GPO_NUM(x) (((x) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CONF_STATUS0_GPI_NUM(x) (((x) & GENMASK(15, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CONF_STATUS0_IBIR_DEPTH(x) (4 << (((x) & GENMASK(7, 6)) >> 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONF_STATUS0_SUPPORTS_DDR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CONF_STATUS0_SEC_MASTER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CONF_STATUS0_DEVS_NUM(x) ((x) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CONF_STATUS1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CONF_STATUS1_IBI_HW_RES(x) ((((x) & GENMASK(31, 28)) >> 28) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CONF_STATUS1_CMD_DEPTH(x) (4 << (((x) & GENMASK(27, 26)) >> 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONF_STATUS1_SLVDDR_RX_DEPTH(x) (8 << (((x) & GENMASK(25, 21)) >> 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CONF_STATUS1_SLVDDR_TX_DEPTH(x) (8 << (((x) & GENMASK(20, 16)) >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CONF_STATUS1_IBI_DEPTH(x) (2 << (((x) & GENMASK(12, 10)) >> 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CONF_STATUS1_RX_DEPTH(x) (8 << (((x) & GENMASK(9, 5)) >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CONF_STATUS1_TX_DEPTH(x) (8 << ((x) & GENMASK(4, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REV_ID 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REV_ID_VID(id) (((id) & GENMASK(31, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REV_ID_PID(id) (((id) & GENMASK(19, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REV_ID_REV_MAJOR(id) (((id) & GENMASK(7, 4)) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REV_ID_REV_MINOR(id) ((id) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CTRL_DEV_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTRL_HALT_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CTRL_MCS BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CTRL_MCS_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CTRL_THD_DELAY(x) (((x) << 24) & GENMASK(25, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CTRL_HJ_DISEC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CTRL_MST_ACK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CTRL_HJ_ACK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CTRL_HJ_INIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CTRL_MST_INIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTRL_AHDR_OPT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTRL_PURE_BUS_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CTRL_MIXED_FAST_BUS_MODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CTRL_MIXED_SLOW_BUS_MODE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CTRL_BUS_MODE_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define THD_DELAY_MAX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PRESCL_CTRL0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PRESCL_CTRL0_I2C(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PRESCL_CTRL0_I3C(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PRESCL_CTRL0_MAX GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PRESCL_CTRL1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PRESCL_CTRL1_PP_LOW_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PRESCL_CTRL1_PP_LOW(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PRESCL_CTRL1_OD_LOW_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PRESCL_CTRL1_OD_LOW(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MST_IER 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MST_IDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MST_IMR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MST_ICR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MST_ISR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MST_INT_HALTED BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MST_INT_MR_DONE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MST_INT_IMM_COMP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MST_INT_TX_THR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MST_INT_TX_OVF BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MST_INT_IBID_THR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MST_INT_IBID_UNF BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MST_INT_IBIR_THR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MST_INT_IBIR_UNF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MST_INT_IBIR_OVF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MST_INT_RX_THR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MST_INT_RX_UNF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MST_INT_CMDD_EMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MST_INT_CMDD_THR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MST_INT_CMDD_OVF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MST_INT_CMDR_THR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MST_INT_CMDR_UNF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MST_INT_CMDR_OVF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MST_STATUS0 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MST_STATUS0_IDLE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MST_STATUS0_HALTED BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MST_STATUS0_MASTER_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MST_STATUS0_TX_FULL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MST_STATUS0_IBID_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MST_STATUS0_IBIR_FULL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MST_STATUS0_RX_FULL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MST_STATUS0_CMDD_FULL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MST_STATUS0_CMDR_FULL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MST_STATUS0_TX_EMP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MST_STATUS0_IBID_EMP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MST_STATUS0_IBIR_EMP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MST_STATUS0_RX_EMP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MST_STATUS0_CMDD_EMP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MST_STATUS0_CMDR_EMP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMDR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CMDR_NO_ERROR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMDR_DDR_PREAMBLE_ERROR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMDR_DDR_PARITY_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMDR_DDR_RX_FIFO_OVF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMDR_DDR_TX_FIFO_UNF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMDR_M0_ERROR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMDR_M1_ERROR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMDR_M2_ERROR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMDR_MST_ABORT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMDR_NACK_RESP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMDR_INVALID_DA 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMDR_DDR_DROPPED 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMDR_ERROR(x) (((x) & GENMASK(27, 24)) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMDR_XFER_BYTES(x) (((x) & GENMASK(19, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMDR_CMDID_HJACK_DISEC 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMDR_CMDID_HJACK_ENTDAA 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMDR_CMDID(x) ((x) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IBIR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IBIR_ACKED BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IBIR_SLVID(x) (((x) & GENMASK(11, 8)) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IBIR_ERROR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IBIR_XFER_BYTES(x) (((x) & GENMASK(6, 2)) >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IBIR_TYPE_IBI 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IBIR_TYPE_HJ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IBIR_TYPE_MR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IBIR_TYPE(x) ((x) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SLV_IER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SLV_IDR 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SLV_IMR 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SLV_ICR 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SLV_ISR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SLV_INT_TM BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SLV_INT_ERROR BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SLV_INT_EVENT_UP BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SLV_INT_HJ_DONE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SLV_INT_MR_DONE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SLV_INT_DA_UPD BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SLV_INT_SDR_FAIL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SLV_INT_DDR_FAIL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SLV_INT_M_RD_ABORT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SLV_INT_DDR_RX_THR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SLV_INT_DDR_TX_THR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SLV_INT_SDR_RX_THR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SLV_INT_SDR_TX_THR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SLV_INT_DDR_RX_UNF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SLV_INT_DDR_TX_OVF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SLV_INT_SDR_RX_UNF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SLV_INT_SDR_TX_OVF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SLV_INT_DDR_RD_COMP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SLV_INT_DDR_WR_COMP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SLV_INT_SDR_RD_COMP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SLV_INT_SDR_WR_COMP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SLV_STATUS0 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SLV_STATUS0_REG_ADDR(s) (((s) & GENMASK(23, 16)) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SLV_STATUS0_XFRD_BYTES(s) ((s) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SLV_STATUS1 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SLV_STATUS1_AS(s) (((s) & GENMASK(21, 20)) >> 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SLV_STATUS1_VEN_TM BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SLV_STATUS1_HJ_DIS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SLV_STATUS1_MR_DIS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SLV_STATUS1_PROT_ERR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SLV_STATUS1_DA(x) (((s) & GENMASK(15, 9)) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SLV_STATUS1_HAS_DA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SLV_STATUS1_DDR_RX_FULL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SLV_STATUS1_DDR_TX_FULL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SLV_STATUS1_DDR_RX_EMPTY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SLV_STATUS1_DDR_TX_EMPTY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SLV_STATUS1_SDR_RX_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SLV_STATUS1_SDR_TX_FULL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SLV_STATUS1_SDR_RX_EMPTY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SLV_STATUS1_SDR_TX_EMPTY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CMD0_FIFO 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CMD0_FIFO_IS_DDR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CMD0_FIFO_IS_CCC BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CMD0_FIFO_BCH BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define XMIT_BURST_STATIC_SUBADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define XMIT_SINGLE_INC_SUBADDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define XMIT_SINGLE_STATIC_SUBADDR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define XMIT_BURST_WITHOUT_SUBADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMD0_FIFO_PRIV_XMIT_MODE(m) ((m) << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CMD0_FIFO_SBCA BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CMD0_FIFO_RSBC BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CMD0_FIFO_IS_10B BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CMD0_FIFO_PL_LEN(l) ((l) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMD0_FIFO_PL_LEN_MAX 4095
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CMD0_FIFO_DEV_ADDR(a) ((a) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CMD0_FIFO_RNW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CMD1_FIFO 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CMD1_FIFO_CMDID(id) ((id) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CMD1_FIFO_CSRADDR(a) (a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CMD1_FIFO_CCC(id) (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TX_FIFO 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMD_CMD0 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMD_CMD0_PL_LEN(l) ((l) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMD_CMD0_DEV_ADDR(a) ((a) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMD_CMD0_RNW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMD_CMD1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMD_CMD1_CCC(id) (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMD_DATA 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define RX_FIFO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IBI_DATA_FIFO 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SLV_DDR_TX_FIFO 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SLV_DDR_RX_FIFO 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CMD_IBI_THR_CTRL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IBIR_THR(t) ((t) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CMDR_THR(t) ((t) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IBI_THR(t) ((t) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CMD_THR(t) (t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TX_RX_THR_CTRL 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RX_THR(t) ((t) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TX_THR(t) (t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SLV_DDR_TX_RX_THR_CTRL 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SLV_DDR_RX_THR(t) ((t) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SLV_DDR_TX_THR(t) (t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define FLUSH_CTRL 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define FLUSH_IBI_RESP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define FLUSH_CMD_RESP BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define FLUSH_SLV_DDR_RX_FIFO BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define FLUSH_SLV_DDR_TX_FIFO BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define FLUSH_IMM_FIFO BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define FLUSH_IBI_FIFO BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define FLUSH_RX_FIFO BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define FLUSH_TX_FIFO BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define FLUSH_CMD_FIFO BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TTO_PRESCL_CTRL0 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TTO_PRESCL_CTRL0_DIVB(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TTO_PRESCL_CTRL0_DIVA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TTO_PRESCL_CTRL1 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TTO_PRESCL_CTRL1_DIVB(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TTO_PRESCL_CTRL1_DIVA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define DEVS_CTRL 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define DEVS_CTRL_DEV_CLR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define DEVS_CTRL_DEV_CLR_ALL GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define DEVS_CTRL_DEV_CLR(dev) BIT(16 + (dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define DEVS_CTRL_DEV_ACTIVE(dev) BIT(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define DEVS_CTRL_DEVS_ACTIVE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MAX_DEVS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define DEV_ID_RR0(d) (0xc0 + ((d) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DEV_ID_RR0_LVR_EXT_ADDR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define DEV_ID_RR0_HDR_CAP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define DEV_ID_RR0_IS_I3C BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DEV_ID_RR0_DEV_ADDR_MASK (GENMASK(6, 0) | GENMASK(15, 13))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DEV_ID_RR0_SET_DEV_ADDR(a) (((a) & GENMASK(6, 0)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) (((a) & GENMASK(9, 7)) << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define DEV_ID_RR0_GET_DEV_ADDR(x) ((((x) >> 1) & GENMASK(6, 0)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) (((x) >> 6) & GENMASK(9, 7)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define DEV_ID_RR1(d) (0xc4 + ((d) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define DEV_ID_RR1_PID_MSB(pid) (pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DEV_ID_RR2(d) (0xc8 + ((d) * 0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define DEV_ID_RR2_PID_LSB(pid) ((pid) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define DEV_ID_RR2_BCR(bcr) ((bcr) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define DEV_ID_RR2_DCR(dcr) (dcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define DEV_ID_RR2_LVR(lvr) (lvr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SIR_MAP(x) (0x180 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SIR_MAP_DEV_REG(d) SIR_MAP((d) / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SIR_MAP_DEV_SHIFT(d, fs) ((fs) + (((d) % 2) ? 16 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SIR_MAP_DEV_CONF_MASK(d) (GENMASK(15, 0) << (((d) % 2) ? 16 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SIR_MAP_DEV_CONF(d, c) ((c) << (((d) % 2) ? 16 : 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define DEV_ROLE_SLAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define DEV_ROLE_MASTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SIR_MAP_DEV_ROLE(role) ((role) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SIR_MAP_DEV_SLOW BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SIR_MAP_DEV_PL(l) ((l) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define SIR_MAP_PL_MAX GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SIR_MAP_DEV_DA(a) ((a) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SIR_MAP_DEV_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GPIR_WORD(x) (0x200 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GPI_REG(val, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GPOR_WORD(x) (0x220 + ((x) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define GPO_REG(val, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (((val) >> (((id) % 4) * 8)) & GENMASK(7, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ASF_INT_STATUS 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define ASF_INT_RAW_STATUS 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define ASF_INT_MASK 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ASF_INT_TEST 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ASF_INT_FATAL_SELECT 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ASF_INTEGRITY_ERR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ASF_PROTOCOL_ERR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ASF_TRANS_TIMEOUT_ERR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ASF_CSR_ERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ASF_DAP_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ASF_SRAM_UNCORR_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ASF_SRAM_CORR_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define ASF_SRAM_CORR_FAULT_STATUS 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define ASF_SRAM_UNCORR_FAULT_STATUS 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define ASF_SRAM_CORR_FAULT_INSTANCE(x) ((x) >> 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define ASF_SRAM_CORR_FAULT_ADDR(x) ((x) & GENMASK(23, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define ASF_SRAM_FAULT_STATS 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ASF_SRAM_FAULT_UNCORR_STATS(x) ((x) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ASF_SRAM_FAULT_CORR_STATS(x) ((x) & GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ASF_TRANS_TOUT_CTRL 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ASF_TRANS_TOUT_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ASF_TRANS_TOUT_VAL(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define ASF_TRANS_TOUT_FAULT_MASK 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define ASF_TRANS_TOUT_FAULT_STATUS 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define ASF_TRANS_TOUT_FAULT_APB BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ASF_TRANS_TOUT_FAULT_SCL_LOW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define ASF_TRANS_TOUT_FAULT_SCL_HIGH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define ASF_TRANS_TOUT_FAULT_FSCL_HIGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define ASF_PROTO_FAULT_MASK 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define ASF_PROTO_FAULT_STATUS 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define ASF_PROTO_FAULT_SLVSDR_RD_ABORT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define ASF_PROTO_FAULT_SLVDDR_FAIL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define ASF_PROTO_FAULT_S(x) BIT(16 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define ASF_PROTO_FAULT_MSTSDR_RD_ABORT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define ASF_PROTO_FAULT_MSTDDR_FAIL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define ASF_PROTO_FAULT_M(x) BIT(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct cdns_i3c_master_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 cmdfifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 cmdrfifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 txfifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u32 rxfifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 ibirfifodepth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct cdns_i3c_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 cmd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 cmd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u32 tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const void *tx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 rx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct cdns_i3c_xfer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int ncmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct cdns_i3c_cmd cmds[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct cdns_i3c_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u8 thd_delay_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct cdns_i3c_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct work_struct hj_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct i3c_master_controller base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 free_rr_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int maxdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct i3c_dev_desc **slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } ibi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct cdns_i3c_xfer *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } xferqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct clk *sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct cdns_i3c_master_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long i3c_scl_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const struct cdns_i3c_data *devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static inline struct cdns_i3c_master *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) to_cdns_i3c_master(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return container_of(master, struct cdns_i3c_master, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) const u8 *bytes, int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) writesl(master->regs + TX_FIFO, bytes, nbytes / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (nbytes & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writesl(master->regs + TX_FIFO, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 *bytes, int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) readsl(master->regs + RX_FIFO, bytes, nbytes / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (nbytes & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) readsl(master->regs + RX_FIFO, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) const struct i3c_ccc_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (cmd->ndests > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (cmd->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case I3C_CCC_ENEC(true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case I3C_CCC_ENEC(false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case I3C_CCC_DISEC(true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case I3C_CCC_DISEC(false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case I3C_CCC_ENTAS(0, true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case I3C_CCC_ENTAS(0, false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case I3C_CCC_RSTDAA(true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case I3C_CCC_RSTDAA(false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case I3C_CCC_ENTDAA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case I3C_CCC_SETMWL(true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case I3C_CCC_SETMWL(false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case I3C_CCC_SETMRL(true):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case I3C_CCC_SETMRL(false):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case I3C_CCC_DEFSLVS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case I3C_CCC_ENTHDR(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case I3C_CCC_SETDASA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case I3C_CCC_SETNEWDA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case I3C_CCC_GETMWL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case I3C_CCC_GETMRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case I3C_CCC_GETPID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case I3C_CCC_GETBCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case I3C_CCC_GETDCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case I3C_CCC_GETSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case I3C_CCC_GETACCMST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case I3C_CCC_GETMXDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case I3C_CCC_GETHDRCAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int cdns_i3c_master_disable(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN, master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return readl_poll_timeout(master->regs + MST_STATUS0, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) status & MST_STATUS0_IDLE, 10, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void cdns_i3c_master_enable(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) writel(readl(master->regs + CTRL) | CTRL_DEV_EN, master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static struct cdns_i3c_xfer *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct cdns_i3c_xfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) INIT_LIST_HEAD(&xfer->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) xfer->ncmds = ncmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) xfer->ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) kfree(xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) writel(MST_INT_CMDD_EMP, master->regs + MST_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) for (i = 0; i < xfer->ncmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cdns_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cmd->tx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (i = 0; i < xfer->ncmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct cdns_i3c_cmd *cmd = &xfer->cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) writel(cmd->cmd1 | CMD1_FIFO_CMDID(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) master->regs + CMD1_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writel(cmd->cmd0, master->regs + CMD0_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) writel(readl(master->regs + CTRL) | CTRL_MCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) writel(MST_INT_CMDD_EMP, master->regs + MST_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct cdns_i3c_xfer *xfer = master->xferqueue.cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!(isr & MST_INT_CMDD_EMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (status0 = readl(master->regs + MST_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) !(status0 & MST_STATUS0_CMDR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) status0 = readl(master->regs + MST_STATUS0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct cdns_i3c_cmd *cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 cmdr, rx_len, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cmdr = readl(master->regs + CMDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) id = CMDR_CMDID(cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (id == CMDR_CMDID_HJACK_DISEC ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) id == CMDR_CMDID_HJACK_ENTDAA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) WARN_ON(id >= xfer->ncmds))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cmd = &xfer->cmds[CMDR_CMDID(cmdr)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rx_len = min_t(u32, CMDR_XFER_BYTES(cmdr), cmd->rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cdns_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) cmd->error = CMDR_ERROR(cmdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) for (i = 0; i < xfer->ncmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) switch (xfer->cmds[i].error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case CMDR_NO_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case CMDR_DDR_PREAMBLE_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) case CMDR_DDR_PARITY_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case CMDR_M0_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case CMDR_M1_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case CMDR_M2_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case CMDR_MST_ABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case CMDR_NACK_RESP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case CMDR_DDR_DROPPED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case CMDR_DDR_RX_FIFO_OVF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case CMDR_DDR_TX_FIFO_UNF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case CMDR_INVALID_DA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) xfer->ret = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) complete(&xfer->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) xfer = list_first_entry_or_null(&master->xferqueue.list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct cdns_i3c_xfer, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) list_del_init(&xfer->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) master->xferqueue.cur = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cdns_i3c_master_start_xfer_locked(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct cdns_i3c_xfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) init_completion(&xfer->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) spin_lock_irqsave(&master->xferqueue.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (master->xferqueue.cur) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) list_add_tail(&xfer->node, &master->xferqueue.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) master->xferqueue.cur = xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) cdns_i3c_master_start_xfer_locked(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) spin_unlock_irqrestore(&master->xferqueue.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct cdns_i3c_xfer *xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_lock_irqsave(&master->xferqueue.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (master->xferqueue.cur == xfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) writel(readl(master->regs + CTRL) & ~CTRL_DEV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) readl_poll_timeout_atomic(master->regs + MST_STATUS0, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) status & MST_STATUS0_IDLE, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) master->xferqueue.cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) writel(FLUSH_RX_FIFO | FLUSH_TX_FIFO | FLUSH_CMD_FIFO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) FLUSH_CMD_RESP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) master->regs + FLUSH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel(MST_INT_CMDD_EMP, master->regs + MST_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) writel(readl(master->regs + CTRL) | CTRL_DEV_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) list_del_init(&xfer->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) spin_unlock_irqrestore(&master->xferqueue.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) switch (cmd->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case CMDR_M0_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return I3C_ERROR_M0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case CMDR_M1_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return I3C_ERROR_M1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case CMDR_M2_ERROR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case CMDR_NACK_RESP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return I3C_ERROR_M2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return I3C_ERROR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct i3c_ccc_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct cdns_i3c_xfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct cdns_i3c_cmd *ccmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) xfer = cdns_i3c_master_alloc_xfer(master, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ccmd = xfer->cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ccmd->cmd1 = CMD1_FIFO_CCC(cmd->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ccmd->cmd0 = CMD0_FIFO_IS_CCC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) CMD0_FIFO_PL_LEN(cmd->dests[0].payload.len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (cmd->id & I3C_CCC_DIRECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ccmd->cmd0 |= CMD0_FIFO_DEV_ADDR(cmd->dests[0].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (cmd->rnw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ccmd->cmd0 |= CMD0_FIFO_RNW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ccmd->rx_buf = cmd->dests[0].payload.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ccmd->rx_len = cmd->dests[0].payload.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ccmd->tx_buf = cmd->dests[0].payload.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ccmd->tx_len = cmd->dests[0].payload.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cdns_i3c_master_queue_xfer(master, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) cdns_i3c_master_unqueue_xfer(master, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = xfer->ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cmd->err = cdns_i3c_cmd_get_err(&xfer->cmds[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) cdns_i3c_master_free_xfer(xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct i3c_priv_xfer *xfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int nxfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int txslots = 0, rxslots = 0, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct cdns_i3c_xfer *cdns_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) for (i = 0; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!nxfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (nxfers > master->caps.cmdfifodepth ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) nxfers > master->caps.cmdrfifodepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * First make sure that all transactions (block of transfers separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * by a STOP marker) fit in the FIFOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (xfers[i].rnw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rxslots += DIV_ROUND_UP(xfers[i].len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) txslots += DIV_ROUND_UP(xfers[i].len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (rxslots > master->caps.rxfifodepth ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) txslots > master->caps.txfifodepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) cdns_xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (!cdns_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) for (i = 0; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct cdns_i3c_cmd *ccmd = &cdns_xfer->cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 pl_len = xfers[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(dev->info.dyn_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (xfers[i].rnw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ccmd->cmd0 |= CMD0_FIFO_RNW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ccmd->rx_buf = xfers[i].data.in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ccmd->rx_len = xfers[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) pl_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ccmd->tx_buf = xfers[i].data.out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ccmd->tx_len = xfers[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ccmd->cmd0 |= CMD0_FIFO_PL_LEN(pl_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (i < nxfers - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ccmd->cmd0 |= CMD0_FIFO_RSBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ccmd->cmd0 |= CMD0_FIFO_BCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) cdns_i3c_master_queue_xfer(master, cdns_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!wait_for_completion_timeout(&cdns_xfer->comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) cdns_i3c_master_unqueue_xfer(master, cdns_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = cdns_xfer->ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = 0; i < nxfers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) xfers[i].err = cdns_i3c_cmd_get_err(&cdns_xfer->cmds[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cdns_i3c_master_free_xfer(cdns_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) const struct i2c_msg *xfers, int nxfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct i3c_master_controller *m = i2c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) unsigned int nrxwords = 0, ntxwords = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct cdns_i3c_xfer *xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (nxfers > master->caps.cmdfifodepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) for (i = 0; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (xfers[i].len > CMD0_FIFO_PL_LEN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (xfers[i].flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) nrxwords += DIV_ROUND_UP(xfers[i].len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ntxwords += DIV_ROUND_UP(xfers[i].len, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (ntxwords > master->caps.txfifodepth ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) nrxwords > master->caps.rxfifodepth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) xfer = cdns_i3c_master_alloc_xfer(master, nxfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (i = 0; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct cdns_i3c_cmd *ccmd = &xfer->cmds[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ccmd->cmd0 = CMD0_FIFO_DEV_ADDR(xfers[i].addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) CMD0_FIFO_PL_LEN(xfers[i].len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) CMD0_FIFO_PRIV_XMIT_MODE(XMIT_BURST_WITHOUT_SUBADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (xfers[i].flags & I2C_M_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ccmd->cmd0 |= CMD0_FIFO_IS_10B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (xfers[i].flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ccmd->cmd0 |= CMD0_FIFO_RNW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ccmd->rx_buf = xfers[i].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ccmd->rx_len = xfers[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ccmd->tx_buf = xfers[i].buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ccmd->tx_len = xfers[i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) cdns_i3c_master_queue_xfer(master, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cdns_i3c_master_unqueue_xfer(master, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = xfer->ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) cdns_i3c_master_free_xfer(xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct cdns_i3c_i2c_dev_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) s16 ibi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct i3c_generic_ibi_pool *ibi_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static u32 prepare_rr0_dev_address(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 ret = (addr << 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* RR0[7:1] = addr[6:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret |= (addr & GENMASK(6, 0)) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* RR0[15:13] = addr[9:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret |= (addr & GENMASK(9, 7)) << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* RR0[0] = ~XOR(addr[6:0]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!(hweight8(addr & 0x7f) & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u32 rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) rr = prepare_rr0_dev_address(dev->info.dyn_addr ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev->info.dyn_addr :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev->info.static_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) writel(DEV_ID_RR0_IS_I3C | rr, master->regs + DEV_ID_RR0(data->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u8 dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned long activedevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!dyn_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (!master->free_rr_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return ffs(master->free_rr_slots) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) activedevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) activedevs &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) for_each_set_bit(i, &activedevs, master->maxdevs + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rr = readl(master->regs + DEV_ID_RR0(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!(rr & DEV_ID_RR0_IS_I3C) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DEV_ID_RR0_GET_DEV_ADDR(rr) != dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u8 old_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cdns_i3c_master_upd_i3c_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct cdns_i3c_i2c_dev_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) slot = cdns_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (slot < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) data->ibi = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) data->id = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) i3c_dev_set_master_data(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) master->free_rr_slots &= ~BIT(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (!dev->info.dyn_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) cdns_i3c_master_upd_i3c_addr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) writel(readl(master->regs + DEVS_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) DEVS_CTRL_DEV_ACTIVE(data->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) writel(readl(master->regs + DEVS_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) DEVS_CTRL_DEV_CLR(data->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) i3c_dev_set_master_data(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) master->free_rr_slots |= BIT(data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct i3c_master_controller *m = i2c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct cdns_i3c_i2c_dev_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) slot = cdns_i3c_master_get_rr_slot(master, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (slot < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) data->id = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) master->free_rr_slots &= ~BIT(slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) i2c_dev_set_master_data(dev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) writel(prepare_rr0_dev_address(dev->addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) master->regs + DEV_ID_RR0(data->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) writel(dev->lvr, master->regs + DEV_ID_RR2(data->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) writel(readl(master->regs + DEVS_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) DEVS_CTRL_DEV_ACTIVE(data->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct i3c_master_controller *m = i2c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct cdns_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) writel(readl(master->regs + DEVS_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DEVS_CTRL_DEV_CLR(data->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) master->free_rr_slots |= BIT(data->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) i2c_dev_set_master_data(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) cdns_i3c_master_disable(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned int slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u32 rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) memset(info, 0, sizeof(*info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) rr = readl(master->regs + DEV_ID_RR0(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) info->dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(rr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) rr = readl(master->regs + DEV_ID_RR2(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) info->dcr = rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) info->bcr = rr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) info->pid = rr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) info->pid |= (u64)readl(master->regs + DEV_ID_RR1(slot)) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct i3c_master_controller *m = &master->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) unsigned long i3c_lim_period, pres_step, ncycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct i3c_bus *bus = i3c_master_get_bus(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned long new_i3c_scl_lim = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct i3c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u32 prescl1, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) i3c_bus_for_each_i3cdev(bus, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned long max_fscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) switch (max_fscl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case I3C_SDR1_FSCL_8MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) max_fscl = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case I3C_SDR2_FSCL_6MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) max_fscl = 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) case I3C_SDR3_FSCL_4MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) max_fscl = 4000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case I3C_SDR4_FSCL_2MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) max_fscl = 2000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) case I3C_SDR0_FSCL_MAX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) max_fscl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (max_fscl &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) (new_i3c_scl_lim > max_fscl || !new_i3c_scl_lim))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) new_i3c_scl_lim = max_fscl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Only update PRESCL_CTRL1 if the I3C SCL limitation has changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (new_i3c_scl_lim == master->i3c_scl_lim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) master->i3c_scl_lim = new_i3c_scl_lim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!new_i3c_scl_lim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) pres_step = 1000000000UL / (bus->scl_rate.i3c * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* Configure PP_LOW to meet I3C slave limitations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) prescl1 = readl(master->regs + PRESCL_CTRL1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ~PRESCL_CTRL1_PP_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ctrl = readl(master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) i3c_lim_period = DIV_ROUND_UP(1000000000, master->i3c_scl_lim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ncycles = DIV_ROUND_UP(i3c_lim_period, pres_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (ncycles < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ncycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ncycles -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) prescl1 |= PRESCL_CTRL1_PP_LOW(ncycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* Disable I3C master before updating PRESCL_CTRL1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (ctrl & CTRL_DEV_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) cdns_i3c_master_disable(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) writel(prescl1, master->regs + PRESCL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (ctrl & CTRL_DEV_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) cdns_i3c_master_enable(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static int cdns_i3c_master_do_daa(struct i3c_master_controller *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unsigned long olddevs, newdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int ret, slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u8 addrs[MAX_DEVS] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u8 last_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) olddevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) olddevs |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Prepare RR slots before launching DAA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for_each_clear_bit(slot, &olddevs, master->maxdevs + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = i3c_master_get_free_addr(m, last_addr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) last_addr = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) addrs[slot] = last_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) writel(prepare_rr0_dev_address(last_addr) | DEV_ID_RR0_IS_I3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) master->regs + DEV_ID_RR0(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) writel(0, master->regs + DEV_ID_RR1(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) writel(0, master->regs + DEV_ID_RR2(slot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = i3c_master_entdaa_locked(&master->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret && ret != I3C_ERROR_M2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) newdevs = readl(master->regs + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) newdevs &= ~olddevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * Clear all retaining registers filled during DAA. We already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * have the addressed assigned to them in the addrs array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) for_each_set_bit(slot, &newdevs, master->maxdevs + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) i3c_master_add_i3c_dev_locked(m, addrs[slot]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * Clear slots that ended up not being used. Can be caused by I3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * device creation failure or when the I3C device was already known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * by the system but with a different address (in this case the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * already has a slot and does not need a new one).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) writel(readl(master->regs + DEVS_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) master->free_rr_slots << DEVS_CTRL_DEV_CLR_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) i3c_master_defslvs_locked(&master->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) cdns_i3c_master_upd_i3c_scl_lim(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Unmask Hot-Join and Mastership request interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) i3c_master_enec_locked(m, I3C_BROADCAST_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) I3C_CCC_EVENT_HJ | I3C_CCC_EVENT_MR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static u8 cdns_i3c_master_calculate_thd_delay(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) unsigned long sysclk_rate = clk_get_rate(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) u8 thd_delay = DIV_ROUND_UP(master->devdata->thd_delay_ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (NSEC_PER_SEC / sysclk_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Every value greater than 3 is not valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (thd_delay > THD_DELAY_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) thd_delay = THD_DELAY_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* CTLR_THD_DEL value is encoded. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return (THD_DELAY_MAX - thd_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int cdns_i3c_master_bus_init(struct i3c_master_controller *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) unsigned long pres_step, sysclk_rate, max_i2cfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct i3c_bus *bus = i3c_master_get_bus(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 ctrl, prescl0, prescl1, pres, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct i3c_device_info info = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int ret, ncycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) switch (bus->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case I3C_BUS_MODE_PURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ctrl = CTRL_PURE_BUS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case I3C_BUS_MODE_MIXED_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ctrl = CTRL_MIXED_FAST_BUS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) case I3C_BUS_MODE_MIXED_SLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ctrl = CTRL_MIXED_SLOW_BUS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) sysclk_rate = clk_get_rate(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!sysclk_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) pres = DIV_ROUND_UP(sysclk_rate, (bus->scl_rate.i3c * 4)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (pres > PRESCL_CTRL0_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) bus->scl_rate.i3c = sysclk_rate / ((pres + 1) * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) prescl0 = PRESCL_CTRL0_I3C(pres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) low = ((I3C_BUS_TLOW_OD_MIN_NS * sysclk_rate) / (pres + 1)) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) prescl1 = PRESCL_CTRL1_OD_LOW(low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) max_i2cfreq = bus->scl_rate.i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) pres = (sysclk_rate / (max_i2cfreq * 5)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (pres > PRESCL_CTRL0_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) bus->scl_rate.i2c = sysclk_rate / ((pres + 1) * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) prescl0 |= PRESCL_CTRL0_I2C(pres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) writel(prescl0, master->regs + PRESCL_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Calculate OD and PP low. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pres_step = 1000000000 / (bus->scl_rate.i3c * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ncycles = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, pres_step) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (ncycles < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ncycles = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) prescl1 = PRESCL_CTRL1_OD_LOW(ncycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) writel(prescl1, master->regs + PRESCL_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Get an address for the master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = i3c_master_get_free_addr(m, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) writel(prepare_rr0_dev_address(ret) | DEV_ID_RR0_IS_I3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) master->regs + DEV_ID_RR0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) cdns_i3c_master_dev_rr_to_info(master, 0, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (info.bcr & I3C_BCR_HDR_CAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) info.hdr_cap = I3C_CCC_HDR_MODE(I3C_HDR_DDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = i3c_master_set_info(&master->base, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * Enable Hot-Join, and, when a Hot-Join request happens, disable all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * events coming from this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * We will issue ENTDAA afterwards from the threaded IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ctrl |= CTRL_HJ_ACK | CTRL_HJ_DISEC | CTRL_HALT_EN | CTRL_MCS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * Configure data hold delay based on device-specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * MIPI I3C Specification 1.0 defines non-zero minimal tHD_PP timing on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * master output. This setting allows to meet this timing on master's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * SoC outputs, regardless of PCB balancing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ctrl |= CTRL_THD_DELAY(cdns_i3c_master_calculate_thd_delay(master));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) writel(ctrl, master->regs + CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) cdns_i3c_master_enable(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 ibir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct cdns_i3c_i2c_dev_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) bool data_consumed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct i3c_ibi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 id = IBIR_SLVID(ibir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct i3c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) size_t nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * FIXME: maybe we should report the FIFO OVF errors to the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * layer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (id >= master->ibi.num_slots || (ibir & IBIR_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev = master->ibi.slots[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) spin_lock(&master->ibi.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) buf = slot->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) nbytes = IBIR_XFER_BYTES(ibir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) readsl(master->regs + IBI_DATA_FIFO, buf, nbytes / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (nbytes % 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) u32 tmp = __raw_readl(master->regs + IBI_DATA_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) slot->len = min_t(unsigned int, IBIR_XFER_BYTES(ibir),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev->ibi->max_payload_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) i3c_master_queue_ibi(dev, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) data_consumed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) spin_unlock(&master->ibi.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Consume data from the FIFO if it's not been done already. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (!data_consumed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) for (i = 0; i < IBIR_XFER_BYTES(ibir); i += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) readl(master->regs + IBI_DATA_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) u32 status0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) writel(MST_INT_IBIR_THR, master->regs + MST_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for (status0 = readl(master->regs + MST_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) !(status0 & MST_STATUS0_IBIR_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) status0 = readl(master->regs + MST_STATUS0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) u32 ibir = readl(master->regs + IBIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) switch (IBIR_TYPE(ibir)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case IBIR_TYPE_IBI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) cdns_i3c_master_handle_ibi(master, ibir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case IBIR_TYPE_HJ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) queue_work(master->base.wq, &master->hj_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) case IBIR_TYPE_MR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) WARN_ON(IBIR_XFER_BYTES(ibir) || (ibir & IBIR_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct cdns_i3c_master *master = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) status = readl(master->regs + MST_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (!(status & readl(master->regs + MST_IMR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) spin_lock(&master->xferqueue.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) cdns_i3c_master_end_xfer_locked(master, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) spin_unlock(&master->xferqueue.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (status & MST_INT_IBIR_THR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) cnds_i3c_master_demux_ibis(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u32 sirmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) I3C_CCC_EVENT_SIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) spin_lock_irqsave(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sirmap |= SIR_MAP_DEV_CONF(data->ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) spin_unlock_irqrestore(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) u32 sircfg, sirmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) spin_lock_irqsave(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sircfg = SIR_MAP_DEV_ROLE(dev->info.bcr >> 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SIR_MAP_DEV_DA(dev->info.dyn_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) SIR_MAP_DEV_PL(dev->info.max_ibi_len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) SIR_MAP_DEV_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) sircfg |= SIR_MAP_DEV_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) sirmap |= SIR_MAP_DEV_CONF(data->ibi, sircfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) spin_unlock_irqrestore(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ret = i3c_master_enec_locked(m, dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) I3C_CCC_EVENT_SIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) spin_lock_irqsave(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) sirmap = readl(master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) sirmap &= ~SIR_MAP_DEV_CONF_MASK(data->ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) sirmap |= SIR_MAP_DEV_CONF(data->ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) SIR_MAP_DEV_DA(I3C_BROADCAST_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) writel(sirmap, master->regs + SIR_MAP_DEV_REG(data->ibi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) spin_unlock_irqrestore(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) const struct i3c_ibi_setup *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (IS_ERR(data->ibi_pool))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return PTR_ERR(data->ibi_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) spin_lock_irqsave(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) for (i = 0; i < master->ibi.num_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!master->ibi.slots[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) data->ibi = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) master->ibi.slots[i] = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) spin_unlock_irqrestore(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (i < master->ibi.num_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) i3c_generic_ibi_free_pool(data->ibi_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) data->ibi_pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) struct i3c_master_controller *m = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct cdns_i3c_master *master = to_cdns_i3c_master(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) spin_lock_irqsave(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) master->ibi.slots[data->ibi] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) data->ibi = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) spin_unlock_irqrestore(&master->ibi.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) i3c_generic_ibi_free_pool(data->ibi_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct i3c_ibi_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct cdns_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const struct i3c_master_controller_ops cdns_i3c_master_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .bus_init = cdns_i3c_master_bus_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .bus_cleanup = cdns_i3c_master_bus_cleanup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .do_daa = cdns_i3c_master_do_daa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .attach_i3c_dev = cdns_i3c_master_attach_i3c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .reattach_i3c_dev = cdns_i3c_master_reattach_i3c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .detach_i3c_dev = cdns_i3c_master_detach_i3c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .attach_i2c_dev = cdns_i3c_master_attach_i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .detach_i2c_dev = cdns_i3c_master_detach_i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .supports_ccc_cmd = cdns_i3c_master_supports_ccc_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .send_ccc_cmd = cdns_i3c_master_send_ccc_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .priv_xfers = cdns_i3c_master_priv_xfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .i2c_xfers = cdns_i3c_master_i2c_xfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .enable_ibi = cdns_i3c_master_enable_ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .disable_ibi = cdns_i3c_master_disable_ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .request_ibi = cdns_i3c_master_request_ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .free_ibi = cdns_i3c_master_free_ibi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .recycle_ibi_slot = cdns_i3c_master_recycle_ibi_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static void cdns_i3c_master_hj(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct cdns_i3c_master *master = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct cdns_i3c_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) hj_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) i3c_master_do_daa(&master->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static struct cdns_i3c_data cdns_i3c_devdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .thd_delay_ns = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static const struct of_device_id cdns_i3c_master_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) { .compatible = "cdns,i3c-master", .data = &cdns_i3c_devdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int cdns_i3c_master_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct cdns_i3c_master *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) master->devdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!master->devdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) master->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (IS_ERR(master->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return PTR_ERR(master->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) master->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (IS_ERR(master->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return PTR_ERR(master->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) master->sysclk = devm_clk_get(&pdev->dev, "sysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (IS_ERR(master->sysclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return PTR_ERR(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ret = clk_prepare_enable(master->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ret = clk_prepare_enable(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (readl(master->regs + DEV_ID) != DEV_ID_I3C_MASTER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) goto err_disable_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) spin_lock_init(&master->xferqueue.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) INIT_LIST_HEAD(&master->xferqueue.list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) INIT_WORK(&master->hj_work, cdns_i3c_master_hj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) writel(0xffffffff, master->regs + MST_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) writel(0xffffffff, master->regs + SLV_IDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ret = devm_request_irq(&pdev->dev, irq, cdns_i3c_master_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dev_name(&pdev->dev), master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) goto err_disable_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) val = readl(master->regs + CONF_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Device ID0 is reserved to describe this master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) master->maxdevs = CONF_STATUS0_DEVS_NUM(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) master->free_rr_slots = GENMASK(master->maxdevs, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) val = readl(master->regs + CONF_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) master->caps.cmdfifodepth = CONF_STATUS1_CMD_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) master->caps.rxfifodepth = CONF_STATUS1_RX_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) master->caps.txfifodepth = CONF_STATUS1_TX_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) master->caps.ibirfifodepth = CONF_STATUS0_IBIR_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) master->caps.cmdrfifodepth = CONF_STATUS0_CMDR_DEPTH(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) spin_lock_init(&master->ibi.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) master->ibi.num_slots = CONF_STATUS1_IBI_HW_RES(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) sizeof(*master->ibi.slots),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (!master->ibi.slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) goto err_disable_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) writel(IBIR_THR(1), master->regs + CMD_IBI_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) writel(MST_INT_IBIR_THR, master->regs + MST_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) writel(DEVS_CTRL_DEV_CLR_ALL, master->regs + DEVS_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret = i3c_master_register(&master->base, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) &cdns_i3c_master_ops, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) goto err_disable_sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) err_disable_sysclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) clk_disable_unprepare(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) err_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) clk_disable_unprepare(master->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static int cdns_i3c_master_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct cdns_i3c_master *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = i3c_master_unregister(&master->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) clk_disable_unprepare(master->sysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) clk_disable_unprepare(master->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static struct platform_driver cdns_i3c_master = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .probe = cdns_i3c_master_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .remove = cdns_i3c_master_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .name = "cdns-i3c-master",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .of_match_table = cdns_i3c_master_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) module_platform_driver(cdns_i3c_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) MODULE_DESCRIPTION("Cadence I3C master driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) MODULE_ALIAS("platform:cdns-i3c-master");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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