^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Cadence Design Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Boris Brezillon <boris.brezillon@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "internals.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static DEFINE_IDR(i3c_bus_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_MUTEX(i3c_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * i3c_bus_maintenance_lock - Lock the bus for a maintenance operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @bus: I3C bus to take the lock on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * This function takes the bus lock so that no other operations can occur on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * the bus. This is needed for all kind of bus maintenance operation, like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - enabling/disabling slave events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - re-triggering DAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - changing the dynamic address of a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - relinquishing mastership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The reason for this kind of locking is that we don't want drivers and core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * logic to rely on I3C device information that could be changed behind their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void i3c_bus_maintenance_lock(struct i3c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) down_write(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * i3c_bus_maintenance_unlock - Release the bus lock after a maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @bus: I3C bus to release the lock on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Should be called when the bus maintenance operation is done. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * i3c_bus_maintenance_lock() for more details on what these maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * operations are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void i3c_bus_maintenance_unlock(struct i3c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) up_write(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * i3c_bus_normaluse_lock - Lock the bus for a normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @bus: I3C bus to take the lock on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * This function takes the bus lock for any operation that is not a maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * operation (see i3c_bus_maintenance_lock() for a non-exhaustive list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * maintenance operations). Basically all communications with I3C devices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * normal operations (HDR, SDR transfers or CCC commands that do not change bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * state or I3C dynamic address).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Note that this lock is not guaranteeing serialization of normal operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * In other words, transfer requests passed to the I3C master can be submitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * in parallel and I3C master drivers have to use their own locking to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * sure two different communications are not inter-mixed, or access to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * output/input queue is not done while the engine is busy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void i3c_bus_normaluse_lock(struct i3c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) down_read(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * i3c_bus_normaluse_unlock - Release the bus lock after a normal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @bus: I3C bus to release the lock on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Should be called when a normal operation is done. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * i3c_bus_normaluse_lock() for more details on what these normal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void i3c_bus_normaluse_unlock(struct i3c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) up_read(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct i3c_master_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) i3c_bus_to_i3c_master(struct i3c_bus *i3cbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return container_of(i3cbus, struct i3c_master_controller, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct i3c_master_controller *dev_to_i3cmaster(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return container_of(dev, struct i3c_master_controller, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct device_type i3c_device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct i3c_bus *dev_to_i3cbus(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i3c_master_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (dev->type == &i3c_device_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return dev_to_i3cdev(dev)->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) master = dev_to_i3cmaster(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return &master->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct i3c_dev_desc *dev_to_i3cdesc(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i3c_master_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (dev->type == &i3c_device_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return dev_to_i3cdev(dev)->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) master = dev_to_i3cmaster(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return master->this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static ssize_t bcr_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) i3c_bus_normaluse_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) desc = dev_to_i3cdesc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = sprintf(buf, "%x\n", desc->info.bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) i3c_bus_normaluse_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static DEVICE_ATTR_RO(bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static ssize_t dcr_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) i3c_bus_normaluse_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) desc = dev_to_i3cdesc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = sprintf(buf, "%x\n", desc->info.dcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) i3c_bus_normaluse_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static DEVICE_ATTR_RO(dcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static ssize_t pid_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) i3c_bus_normaluse_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) desc = dev_to_i3cdesc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = sprintf(buf, "%llx\n", desc->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) i3c_bus_normaluse_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static DEVICE_ATTR_RO(pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static ssize_t dynamic_address_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i3c_bus_normaluse_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) desc = dev_to_i3cdesc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = sprintf(buf, "%02x\n", desc->info.dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) i3c_bus_normaluse_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static DEVICE_ATTR_RO(dynamic_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const char * const hdrcap_strings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "hdr-ddr", "hdr-tsp", "hdr-tsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static ssize_t hdrcap_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ssize_t offset = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) i3c_bus_normaluse_lock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) desc = dev_to_i3cdesc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) caps = desc->info.hdr_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) for_each_set_bit(mode, &caps, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (mode >= ARRAY_SIZE(hdrcap_strings))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!hdrcap_strings[mode])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = sprintf(buf + offset, offset ? " %s" : "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hdrcap_strings[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) offset += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = sprintf(buf + offset, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = offset + ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) i3c_bus_normaluse_unlock(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static DEVICE_ATTR_RO(hdrcap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static ssize_t modalias_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct device_attribute *da, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct i3c_device *i3c = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct i3c_device_info devinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u16 manuf, part, ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) i3c_device_get_info(i3c, &devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) manuf = I3C_PID_MANUF_ID(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) part = I3C_PID_PART_ID(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ext = I3C_PID_EXTRA_INFO(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (I3C_PID_RND_LOWER_32BITS(devinfo.pid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return sprintf(buf, "i3c:dcr%02Xmanuf%04X", devinfo.dcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) manuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return sprintf(buf, "i3c:dcr%02Xmanuf%04Xpart%04Xext%04X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) devinfo.dcr, manuf, part, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static DEVICE_ATTR_RO(modalias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct attribute *i3c_device_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) &dev_attr_bcr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) &dev_attr_dcr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) &dev_attr_pid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) &dev_attr_dynamic_address.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) &dev_attr_hdrcap.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) &dev_attr_modalias.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ATTRIBUTE_GROUPS(i3c_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int i3c_device_uevent(struct device *dev, struct kobj_uevent_env *env)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct i3c_device *i3cdev = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct i3c_device_info devinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u16 manuf, part, ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) i3c_device_get_info(i3cdev, &devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) manuf = I3C_PID_MANUF_ID(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) part = I3C_PID_PART_ID(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ext = I3C_PID_EXTRA_INFO(devinfo.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (I3C_PID_RND_LOWER_32BITS(devinfo.pid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return add_uevent_var(env, "MODALIAS=i3c:dcr%02Xmanuf%04X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) devinfo.dcr, manuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return add_uevent_var(env,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "MODALIAS=i3c:dcr%02Xmanuf%04Xpart%04Xext%04X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) devinfo.dcr, manuf, part, ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct device_type i3c_device_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .groups = i3c_device_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .uevent = i3c_device_uevent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int i3c_device_match(struct device *dev, struct device_driver *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct i3c_device *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i3c_driver *i3cdrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (dev->type != &i3c_device_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) i3cdev = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i3cdrv = drv_to_i3cdrv(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (i3c_device_match_id(i3cdev, i3cdrv->id_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int i3c_device_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct i3c_device *i3cdev = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return driver->probe(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int i3c_device_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct i3c_device *i3cdev = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct i3c_driver *driver = drv_to_i3cdrv(dev->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = driver->remove(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) i3c_device_free_ibi(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct bus_type i3c_bus_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = "i3c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .match = i3c_device_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .probe = i3c_device_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .remove = i3c_device_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static enum i3c_addr_slot_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) i3c_bus_get_addr_slot_status(struct i3c_bus *bus, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int status, bitpos = addr * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (addr > I2C_MAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return I3C_ADDR_SLOT_RSVD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) status = bus->addrslots[bitpos / BITS_PER_LONG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) status >>= bitpos % BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return status & I3C_ADDR_SLOT_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void i3c_bus_set_addr_slot_status(struct i3c_bus *bus, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) enum i3c_addr_slot_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int bitpos = addr * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (addr > I2C_MAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ptr = bus->addrslots + (bitpos / BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) *ptr &= ~((unsigned long)I3C_ADDR_SLOT_STATUS_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (bitpos % BITS_PER_LONG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *ptr |= (unsigned long)status << (bitpos % BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static bool i3c_bus_dev_addr_is_avail(struct i3c_bus *bus, u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) enum i3c_addr_slot_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) status = i3c_bus_get_addr_slot_status(bus, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return status == I3C_ADDR_SLOT_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int i3c_bus_get_free_addr(struct i3c_bus *bus, u8 start_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) enum i3c_addr_slot_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) for (addr = start_addr; addr < I3C_MAX_ADDR; addr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) status = i3c_bus_get_addr_slot_status(bus, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (status == I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void i3c_bus_init_addrslots(struct i3c_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Addresses 0 to 7 are reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i3c_bus_set_addr_slot_status(bus, i, I3C_ADDR_SLOT_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * Reserve broadcast address and all addresses that might collide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * with the broadcast address when facing a single bit error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) I3C_ADDR_SLOT_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < 7; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) i3c_bus_set_addr_slot_status(bus, I3C_BROADCAST_ADDR ^ BIT(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) I3C_ADDR_SLOT_RSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void i3c_bus_cleanup(struct i3c_bus *i3cbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mutex_lock(&i3c_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) idr_remove(&i3c_bus_idr, i3cbus->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) mutex_unlock(&i3c_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int i3c_bus_init(struct i3c_bus *i3cbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) init_rwsem(&i3cbus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) INIT_LIST_HEAD(&i3cbus->devs.i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) INIT_LIST_HEAD(&i3cbus->devs.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) i3c_bus_init_addrslots(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i3cbus->mode = I3C_BUS_MODE_PURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_lock(&i3c_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = idr_alloc(&i3c_bus_idr, i3cbus, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mutex_unlock(&i3c_core_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i3cbus->id = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const char * const i3c_bus_mode_strings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [I3C_BUS_MODE_PURE] = "pure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [I3C_BUS_MODE_MIXED_FAST] = "mixed-fast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [I3C_BUS_MODE_MIXED_LIMITED] = "mixed-limited",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [I3C_BUS_MODE_MIXED_SLOW] = "mixed-slow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static ssize_t mode_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i3c_bus_normaluse_lock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (i3cbus->mode < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) i3cbus->mode >= ARRAY_SIZE(i3c_bus_mode_strings) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) !i3c_bus_mode_strings[i3cbus->mode])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ret = sprintf(buf, "unknown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = sprintf(buf, "%s\n", i3c_bus_mode_strings[i3cbus->mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) i3c_bus_normaluse_unlock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static DEVICE_ATTR_RO(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static ssize_t current_master_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i3c_bus_normaluse_lock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = sprintf(buf, "%d-%llx\n", i3cbus->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i3cbus->cur_master->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) i3c_bus_normaluse_unlock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static DEVICE_ATTR_RO(current_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static ssize_t i3c_scl_frequency_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) i3c_bus_normaluse_lock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) i3c_bus_normaluse_unlock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static DEVICE_ATTR_RO(i3c_scl_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static ssize_t i2c_scl_frequency_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct device_attribute *da,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct i3c_bus *i3cbus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ssize_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i3c_bus_normaluse_lock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = sprintf(buf, "%ld\n", i3cbus->scl_rate.i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) i3c_bus_normaluse_unlock(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static DEVICE_ATTR_RO(i2c_scl_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct attribute *i3c_masterdev_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &dev_attr_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &dev_attr_current_master.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &dev_attr_i3c_scl_frequency.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &dev_attr_i2c_scl_frequency.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &dev_attr_bcr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &dev_attr_dcr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &dev_attr_pid.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &dev_attr_dynamic_address.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &dev_attr_hdrcap.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ATTRIBUTE_GROUPS(i3c_masterdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void i3c_masterdev_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct i3c_master_controller *master = dev_to_i3cmaster(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct i3c_bus *bus = dev_to_i3cbus(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (master->wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) destroy_workqueue(master->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) i3c_bus_cleanup(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) of_node_put(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct device_type i3c_masterdev_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .groups = i3c_masterdev_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int i3c_bus_set_mode(struct i3c_bus *i3cbus, enum i3c_bus_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long max_i2c_scl_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct i3c_master_controller *master = i3c_bus_to_i3c_master(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) i3cbus->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) switch (i3cbus->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case I3C_BUS_MODE_PURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!i3cbus->scl_rate.i3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case I3C_BUS_MODE_MIXED_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case I3C_BUS_MODE_MIXED_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!i3cbus->scl_rate.i3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) i3cbus->scl_rate.i3c = I3C_BUS_TYP_I3C_SCL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!i3cbus->scl_rate.i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i3cbus->scl_rate.i2c = max_i2c_scl_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case I3C_BUS_MODE_MIXED_SLOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!i3cbus->scl_rate.i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) i3cbus->scl_rate.i2c = max_i2c_scl_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!i3cbus->scl_rate.i3c ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) i3cbus->scl_rate.i3c > i3cbus->scl_rate.i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) i3cbus->scl_rate.i3c = i3cbus->scl_rate.i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_dbg(&master->dev, "i2c-scl = %ld Hz i3c-scl = %ld Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) i3cbus->scl_rate.i2c, i3cbus->scl_rate.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * I3C/I2C frequency may have been overridden, check that user-provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * values are not exceeding max possible frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (i3cbus->scl_rate.i3c > I3C_BUS_MAX_I3C_SCL_RATE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) i3cbus->scl_rate.i2c > I3C_BUS_I2C_FM_PLUS_SCL_RATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct i3c_master_controller *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) i2c_adapter_to_i3c_master(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return container_of(adap, struct i3c_master_controller, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct i2c_adapter *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) i3c_master_to_i2c_adapter(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return &master->i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static void i3c_master_free_i2c_dev(struct i2c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static struct i2c_dev_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) i3c_master_alloc_i2c_dev(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) const struct i2c_dev_boardinfo *boardinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct i2c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev->common.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev->boardinfo = boardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev->addr = boardinfo->base.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev->lvr = boardinfo->lvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static void *i3c_ccc_cmd_dest_init(struct i3c_ccc_cmd_dest *dest, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u16 payloadlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dest->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dest->payload.len = payloadlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (payloadlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dest->payload.data = kzalloc(payloadlen, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dest->payload.data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return dest->payload.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void i3c_ccc_cmd_dest_cleanup(struct i3c_ccc_cmd_dest *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) kfree(dest->payload.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void i3c_ccc_cmd_init(struct i3c_ccc_cmd *cmd, bool rnw, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct i3c_ccc_cmd_dest *dests,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int ndests)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) cmd->rnw = rnw ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cmd->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cmd->dests = dests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) cmd->ndests = ndests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) cmd->err = I3C_ERROR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int i3c_master_send_ccc_cmd_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct i3c_ccc_cmd *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!cmd || !master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (WARN_ON(master->init_done &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) !rwsem_is_locked(&master->bus.lock)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!master->ops->send_ccc_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((cmd->id & I3C_CCC_DIRECT) && (!cmd->dests || !cmd->ndests))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (master->ops->supports_ccc_cmd &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) !master->ops->supports_ccc_cmd(master, cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = master->ops->send_ccc_cmd(master, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (cmd->err != I3C_ERROR_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return cmd->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct i2c_dev_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i3c_master_find_i2c_dev_by_addr(const struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct i2c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) i3c_bus_for_each_i2cdev(&master->bus, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (dev->boardinfo->base.addr == addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * i3c_master_get_free_addr() - get a free address on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @master: I3C master object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @start_addr: where to start searching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Return: the first free address starting at @start_addr (included) or -ENOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * if there's no more address available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int i3c_master_get_free_addr(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u8 start_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return i3c_bus_get_free_addr(&master->bus, start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) EXPORT_SYMBOL_GPL(i3c_master_get_free_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static void i3c_device_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct i3c_device *i3cdev = dev_to_i3cdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) WARN_ON(i3cdev->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) of_node_put(i3cdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) kfree(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void i3c_master_free_i3c_dev(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct i3c_dev_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) i3c_master_alloc_i3c_dev(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) const struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct i3c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev = kzalloc(sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev->common.master = master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev->info = *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_init(&dev->ibi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int i3c_master_rstdaa_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) enum i3c_addr_slot_status addrstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) addrstat = i3c_bus_get_addr_slot_status(&master->bus, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (addr != I3C_BROADCAST_ADDR && addrstat != I3C_ADDR_SLOT_I3C_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) i3c_ccc_cmd_dest_init(&dest, addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) i3c_ccc_cmd_init(&cmd, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) I3C_CCC_RSTDAA(addr == I3C_BROADCAST_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * procedure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Send a ENTDAA CCC command to start a DAA procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * Note that this function only sends the ENTDAA CCC command, all the logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * behind dynamic address assignment has to be handled in the I3C master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * Return: 0 in case of success, a positive I3C error code if the error is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * one of the official Mx error codes, and a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int i3c_master_entdaa_locked(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) i3c_ccc_cmd_init(&cmd, false, I3C_CCC_ENTDAA, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) EXPORT_SYMBOL_GPL(i3c_master_entdaa_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int i3c_master_enec_disec_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u8 addr, bool enable, u8 evts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct i3c_ccc_events *events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) events = i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*events));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) events->events = evts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) i3c_ccc_cmd_init(&cmd, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) enable ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) I3C_CCC_ENEC(addr == I3C_BROADCAST_ADDR) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) I3C_CCC_DISEC(addr == I3C_BROADCAST_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * i3c_master_disec_locked() - send a DISEC CCC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * @evts: events to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Send a DISEC CCC command to disable some or all events coming from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * Return: 0 in case of success, a positive I3C error code if the error is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * one of the official Mx error codes, and a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u8 evts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return i3c_master_enec_disec_locked(master, addr, false, evts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) EXPORT_SYMBOL_GPL(i3c_master_disec_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * i3c_master_enec_locked() - send an ENEC CCC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * @addr: a valid I3C slave address or %I3C_BROADCAST_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * @evts: events to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * Sends an ENEC CCC command to enable some or all events coming from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * specific slave, or all devices if @addr is %I3C_BROADCAST_ADDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * Return: 0 in case of success, a positive I3C error code if the error is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * one of the official Mx error codes, and a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u8 evts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return i3c_master_enec_disec_locked(master, addr, true, evts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) EXPORT_SYMBOL_GPL(i3c_master_enec_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * i3c_master_defslvs_locked() - send a DEFSLVS CCC command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * Send a DEFSLVS CCC command containing all the devices known to the @master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * This is useful when you have secondary masters on the bus to propagate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * This should be called after all I3C devices have been discovered (in other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * words, after the DAA procedure has finished) and instantiated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * &i3c_master_controller_ops->bus_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * It should also be called if a master ACKed an Hot-Join request and assigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * a dynamic address to the device joining the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Return: 0 in case of success, a positive I3C error code if the error is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * one of the official Mx error codes, and a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) int i3c_master_defslvs_locked(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct i3c_ccc_defslvs *defslvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct i3c_ccc_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct i3c_dev_desc *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct i2c_dev_desc *i2cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct i3c_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) bool send = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int ndevs = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) bus = i3c_master_get_bus(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) i3c_bus_for_each_i3cdev(bus, i3cdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ndevs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (i3cdev == master->this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (I3C_BCR_DEVICE_ROLE(i3cdev->info.bcr) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) I3C_BCR_I3C_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) send = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* No other master on the bus, skip DEFSLVS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!send)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) i3c_bus_for_each_i2cdev(bus, i2cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ndevs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) defslvs = i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct_size(defslvs, slaves,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ndevs - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!defslvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) defslvs->count = ndevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) defslvs->master.bcr = master->this->info.bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) defslvs->master.dcr = master->this->info.dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) defslvs->master.dyn_addr = master->this->info.dyn_addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) defslvs->master.static_addr = I3C_BROADCAST_ADDR << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) desc = defslvs->slaves;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) i3c_bus_for_each_i2cdev(bus, i2cdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) desc->lvr = i2cdev->lvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) desc->static_addr = i2cdev->addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) i3c_bus_for_each_i3cdev(bus, i3cdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Skip the I3C dev representing this master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (i3cdev == master->this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) desc->bcr = i3cdev->info.bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) desc->dcr = i3cdev->info.dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) desc->dyn_addr = i3cdev->info.dyn_addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) desc->static_addr = i3cdev->info.static_addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) desc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) i3c_ccc_cmd_init(&cmd, false, I3C_CCC_DEFSLVS, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) EXPORT_SYMBOL_GPL(i3c_master_defslvs_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int i3c_master_setda_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u8 oldaddr, u8 newaddr, bool setdasa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct i3c_ccc_setda *setda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!oldaddr || !newaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) setda = i3c_ccc_cmd_dest_init(&dest, oldaddr, sizeof(*setda));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!setda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) setda->addr = newaddr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) i3c_ccc_cmd_init(&cmd, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) setdasa ? I3C_CCC_SETDASA : I3C_CCC_SETNEWDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int i3c_master_setdasa_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u8 static_addr, u8 dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return i3c_master_setda_locked(master, static_addr, dyn_addr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static int i3c_master_setnewda_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u8 oldaddr, u8 newaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return i3c_master_setda_locked(master, oldaddr, newaddr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int i3c_master_getmrl_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct i3c_ccc_mrl *mrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mrl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!mrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * When the device does not have IBI payload GETMRL only returns 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * bytes of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!(info->bcr & I3C_BCR_IBI_PAYLOAD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dest.payload.len -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMRL, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) switch (dest.payload.len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) info->max_ibi_len = mrl->ibi_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) info->max_read_len = be16_to_cpu(mrl->read_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int i3c_master_getmwl_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct i3c_ccc_mwl *mwl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) mwl = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*mwl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!mwl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMWL, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (dest.payload.len != sizeof(*mwl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) info->max_write_len = be16_to_cpu(mwl->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static int i3c_master_getmxds_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct i3c_ccc_getmxds *getmaxds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) getmaxds = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) sizeof(*getmaxds));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!getmaxds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETMXDS, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (dest.payload.len != 2 && dest.payload.len != 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) info->max_read_ds = getmaxds->maxrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) info->max_write_ds = getmaxds->maxwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (dest.payload.len == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) info->max_read_turnaround = getmaxds->maxrdturn[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ((u32)getmaxds->maxrdturn[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ((u32)getmaxds->maxrdturn[2] << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int i3c_master_gethdrcap_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct i3c_ccc_gethdrcap *gethdrcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) gethdrcap = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) sizeof(*gethdrcap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!gethdrcap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETHDRCAP, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (dest.payload.len != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) info->hdr_cap = gethdrcap->modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int i3c_master_getpid_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct i3c_ccc_getpid *getpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) getpid = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getpid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (!getpid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETPID, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) info->pid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) for (i = 0; i < sizeof(getpid->pid); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) int sft = (sizeof(getpid->pid) - i - 1) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) info->pid |= (u64)getpid->pid[i] << sft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static int i3c_master_getbcr_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct i3c_ccc_getbcr *getbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) getbcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getbcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!getbcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETBCR, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) info->bcr = getbcr->bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static int i3c_master_getdcr_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) struct i3c_ccc_getdcr *getdcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) struct i3c_ccc_cmd_dest dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct i3c_ccc_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) getdcr = i3c_ccc_cmd_dest_init(&dest, info->dyn_addr, sizeof(*getdcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!getdcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETDCR, &dest, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = i3c_master_send_ccc_cmd_locked(master, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) info->dcr = getdcr->dcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) i3c_ccc_cmd_dest_cleanup(&dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int i3c_master_retrieve_dev_info(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) enum i3c_addr_slot_status slot_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!dev->info.dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) slot_status = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev->info.dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (slot_status == I3C_ADDR_SLOT_RSVD ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) slot_status == I3C_ADDR_SLOT_I2C_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = i3c_master_getpid_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = i3c_master_getbcr_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = i3c_master_getdcr_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (dev->info.bcr & I3C_BCR_MAX_DATA_SPEED_LIM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ret = i3c_master_getmxds_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev->info.max_ibi_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) i3c_master_getmrl_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) i3c_master_getmwl_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (dev->info.bcr & I3C_BCR_HDR_CAP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = i3c_master_gethdrcap_locked(master, &dev->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (dev->info.static_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) dev->info.static_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (dev->info.dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (dev->boardinfo && dev->boardinfo->init_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static int i3c_master_get_i3c_addrs(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) enum i3c_addr_slot_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!dev->info.static_addr && !dev->info.dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (dev->info.static_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) status = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev->info.static_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (status != I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev->info.static_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) I3C_ADDR_SLOT_I3C_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * ->init_dyn_addr should have been reserved before that, so, if we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * trying to apply a pre-reserved dynamic address, we should not try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * to reserve the address slot a second time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (dev->info.dyn_addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) (!dev->boardinfo ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev->boardinfo->init_dyn_addr != dev->info.dyn_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) status = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev->info.dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (status != I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) goto err_release_static_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) i3c_bus_set_addr_slot_status(&master->bus, dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) I3C_ADDR_SLOT_I3C_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) err_release_static_addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (dev->info.static_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev->info.static_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static int i3c_master_attach_i3c_dev(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * We don't attach devices to the controller until they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * addressable on the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (!dev->info.static_addr && !dev->info.dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = i3c_master_get_i3c_addrs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* Do not attach the master device itself. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (master->this != dev && master->ops->attach_i3c_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ret = master->ops->attach_i3c_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) i3c_master_put_i3c_addrs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) list_add_tail(&dev->common.node, &master->bus.devs.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) u8 old_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) enum i3c_addr_slot_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (dev->info.dyn_addr != old_dyn_addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) (!dev->boardinfo ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev->info.dyn_addr != dev->boardinfo->init_dyn_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) status = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) dev->info.dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (status != I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) dev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) I3C_ADDR_SLOT_I3C_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (master->ops->reattach_i3c_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = master->ops->reattach_i3c_dev(dev, old_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) i3c_master_put_i3c_addrs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static void i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* Do not detach the master device itself. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (master->this != dev && master->ops->detach_i3c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) master->ops->detach_i3c_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) i3c_master_put_i3c_addrs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) list_del(&dev->common.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static int i3c_master_attach_i2c_dev(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct i2c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (master->ops->attach_i2c_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = master->ops->attach_i2c_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) list_add_tail(&dev->common.node, &master->bus.devs.i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static void i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct i3c_master_controller *master = i2c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) list_del(&dev->common.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (master->ops->detach_i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) master->ops->detach_i2c_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int i3c_master_early_i3c_dev_add(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct i3c_dev_boardinfo *boardinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct i3c_device_info info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .static_addr = boardinfo->static_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct i3c_dev_desc *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) i3cdev = i3c_master_alloc_i3c_dev(master, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (IS_ERR(i3cdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) i3cdev->boardinfo = boardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = i3c_master_attach_i3c_dev(master, i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ret = i3c_master_setdasa_locked(master, i3cdev->info.static_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) i3cdev->boardinfo->init_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) goto err_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) i3cdev->info.dyn_addr = i3cdev->boardinfo->init_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = i3c_master_reattach_i3c_dev(i3cdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto err_rstdaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = i3c_master_retrieve_dev_info(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) goto err_rstdaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) err_rstdaa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) i3c_master_rstdaa_locked(master, i3cdev->boardinfo->init_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) err_detach_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) i3c_master_detach_i3c_dev(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) err_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) i3c_master_free_i3c_dev(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) struct i3c_dev_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (!master->init_done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) i3c_bus_for_each_i3cdev(&master->bus, desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (desc->dev || !desc->info.dyn_addr || desc == master->this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) desc->dev = kzalloc(sizeof(*desc->dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!desc->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) desc->dev->bus = &master->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) desc->dev->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) desc->dev->dev.parent = &master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) desc->dev->dev.type = &i3c_device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) desc->dev->dev.bus = &i3c_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) desc->dev->dev.release = i3c_device_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) desc->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (desc->boardinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) desc->dev->dev.of_node = desc->boardinfo->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ret = device_register(&desc->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) dev_err(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) "Failed to add I3C device (err = %d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * @master: master doing the DAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * This function is instantiating an I3C device object and adding it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) * I3C device list. All device information are automatically retrieved using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * standard CCC commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * The I3C device object is returned in case the master wants to attach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * private data to it using i3c_dev_set_master_data().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * Return: a 0 in case of success, an negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) int i3c_master_do_daa(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) i3c_bus_maintenance_lock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ret = master->ops->do_daa(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) i3c_bus_maintenance_unlock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) i3c_bus_normaluse_lock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) i3c_master_register_new_i3c_devs(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) i3c_bus_normaluse_unlock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) EXPORT_SYMBOL_GPL(i3c_master_do_daa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * i3c_master_set_info() - set master device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * @info: I3C device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * Set master device info. This should be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) * &i3c_master_controller_ops->bus_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * Not all &i3c_device_info fields are meaningful for a master device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) * Here is a list of fields that should be properly filled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * - &i3c_device_info->dyn_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * - &i3c_device_info->bcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * - &i3c_device_info->dcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * - &i3c_device_info->pid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * - &i3c_device_info->hdr_cap if %I3C_BCR_HDR_CAP bit is set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * &i3c_device_info->bcr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * This function must be called with the bus lock held in maintenance mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) * Return: 0 if @info contains valid information (not every piece of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) * information can be checked, but we can at least make sure @info->dyn_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * and @info->bcr are correct), -EINVAL otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int i3c_master_set_info(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) const struct i3c_device_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct i3c_dev_desc *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (!i3c_bus_dev_addr_is_avail(&master->bus, info->dyn_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (I3C_BCR_DEVICE_ROLE(info->bcr) == I3C_BCR_I3C_MASTER &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) master->secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (master->this)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) i3cdev = i3c_master_alloc_i3c_dev(master, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (IS_ERR(i3cdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return PTR_ERR(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) master->this = i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) master->bus.cur_master = master->this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ret = i3c_master_attach_i3c_dev(master, i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) err_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) i3c_master_free_i3c_dev(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) EXPORT_SYMBOL_GPL(i3c_master_set_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static void i3c_master_detach_free_devs(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct i3c_dev_desc *i3cdev, *i3ctmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) struct i2c_dev_desc *i2cdev, *i2ctmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) list_for_each_entry_safe(i3cdev, i3ctmp, &master->bus.devs.i3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) common.node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) i3c_master_detach_i3c_dev(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (i3cdev->boardinfo && i3cdev->boardinfo->init_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) i3cdev->boardinfo->init_dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) i3c_master_free_i3c_dev(i3cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) list_for_each_entry_safe(i2cdev, i2ctmp, &master->bus.devs.i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) common.node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) i3c_master_detach_i2c_dev(i2cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) i2cdev->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) I3C_ADDR_SLOT_FREE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) i3c_master_free_i2c_dev(i2cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * i3c_master_bus_init() - initialize an I3C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * @master: main master initializing the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * This function is following all initialisation steps described in the I3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * specification:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * 1. Attach I2C devs to the master so that the master can fill its internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * device table appropriately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) * 2. Call &i3c_master_controller_ops->bus_init() method to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * the master controller. That's usually where the bus mode is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) * (pure bus or mixed fast/slow bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * 3. Instruct all devices on the bus to drop their dynamic address. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) * particularly important when the bus was previously configured by someone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) * else (for example the bootloader)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) * 4. Disable all slave events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * 5. Reserve address slots for I3C devices with init_dyn_addr. And if devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * also have static_addr, try to pre-assign dynamic addresses requested by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * the FW with SETDASA and attach corresponding statically defined I3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * devices to the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * 6. Do a DAA (Dynamic Address Assignment) to assign dynamic addresses to all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) * remaining I3C devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) * Once this is done, all I3C and I2C devices should be usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * Return: a 0 in case of success, an negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static int i3c_master_bus_init(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) enum i3c_addr_slot_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct i2c_dev_boardinfo *i2cboardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) struct i3c_dev_boardinfo *i3cboardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct i2c_dev_desc *i2cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * First attach all devices with static definitions provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * FW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) list_for_each_entry(i2cboardinfo, &master->boardinfo.i2c, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) status = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) i2cboardinfo->base.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (status != I3C_ADDR_SLOT_FREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) goto err_detach_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) i2cboardinfo->base.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) I3C_ADDR_SLOT_I2C_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) i2cdev = i3c_master_alloc_i2c_dev(master, i2cboardinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (IS_ERR(i2cdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = PTR_ERR(i2cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) goto err_detach_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret = i3c_master_attach_i2c_dev(master, i2cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) i3c_master_free_i2c_dev(i2cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) goto err_detach_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) * Now execute the controller specific ->bus_init() routine, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * might configure its internal logic to match the bus limitations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = master->ops->bus_init(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) goto err_detach_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * The master device should have been instantiated in ->bus_init(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * complain if this was not the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (!master->this) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dev_err(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) "master_set_info() was not called in ->bus_init()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) goto err_bus_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) * Reset all dynamic address that may have been assigned before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) * (assigned by the bootloader for example).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ret = i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (ret && ret != I3C_ERROR_M2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) goto err_bus_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* Disable all slave events before starting DAA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ret = i3c_master_disec_locked(master, I3C_BROADCAST_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) I3C_CCC_EVENT_SIR | I3C_CCC_EVENT_MR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) I3C_CCC_EVENT_HJ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) if (ret && ret != I3C_ERROR_M2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) goto err_bus_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) * Reserve init_dyn_addr first, and then try to pre-assign dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) * address and retrieve device information if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) * In case pre-assign dynamic address fails, setting dynamic address to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) * the requested init_dyn_addr is retried after DAA is done in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) * i3c_master_add_i3c_dev_locked().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * We don't reserve a dynamic address for devices that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * don't explicitly request one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (!i3cboardinfo->init_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ret = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) i3cboardinfo->init_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (ret != I3C_ADDR_SLOT_FREE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) goto err_rstdaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) i3c_bus_set_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) i3cboardinfo->init_dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) I3C_ADDR_SLOT_I3C_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) * Only try to create/attach devices that have a static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * address. Other devices will be created/attached when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * DAA happens, and the requested dynamic address will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) * be set using SETNEWDA once those devices become
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * addressable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (i3cboardinfo->static_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) i3c_master_early_i3c_dev_add(master, i3cboardinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ret = i3c_master_do_daa(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) goto err_rstdaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) err_rstdaa:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) err_bus_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (master->ops->bus_cleanup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) master->ops->bus_cleanup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) err_detach_devs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) i3c_master_detach_free_devs(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static void i3c_master_bus_cleanup(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (master->ops->bus_cleanup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) master->ops->bus_cleanup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) i3c_master_detach_free_devs(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) static void i3c_master_attach_boardinfo(struct i3c_dev_desc *i3cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) struct i3c_master_controller *master = i3cdev->common.master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) struct i3c_dev_boardinfo *i3cboardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (i3cdev->info.pid != i3cboardinfo->pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) i3cdev->boardinfo = i3cboardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) i3cdev->info.static_addr = i3cboardinfo->static_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static struct i3c_dev_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) i3c_master_search_i3c_dev_duplicate(struct i3c_dev_desc *refdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct i3c_master_controller *master = i3c_dev_get_master(refdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct i3c_dev_desc *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (i3cdev != refdev && i3cdev->info.pid == refdev->info.pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * @addr: I3C slave dynamic address assigned to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * This function is instantiating an I3C device object and adding it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * I3C device list. All device information are automatically retrieved using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * standard CCC commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * The I3C device object is returned in case the master wants to attach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * private data to it using i3c_dev_set_master_data().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) * This function must be called with the bus lock held in write mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) * Return: a 0 in case of success, an negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) struct i3c_device_info info = { .dyn_addr = addr };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct i3c_dev_desc *newdev, *olddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) u8 old_dyn_addr = addr, expected_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) struct i3c_ibi_setup ibireq = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) bool enable_ibi = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) newdev = i3c_master_alloc_i3c_dev(master, &info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (IS_ERR(newdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return PTR_ERR(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ret = i3c_master_attach_i3c_dev(master, newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ret = i3c_master_retrieve_dev_info(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) goto err_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) i3c_master_attach_boardinfo(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) olddev = i3c_master_search_i3c_dev_duplicate(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (olddev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) newdev->dev = olddev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (newdev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) newdev->dev->desc = newdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * We need to restore the IBI state too, so let's save the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) * IBI information and try to restore them after olddev has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * been detached+released and its IBI has been stopped and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * the associated resources have been freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) mutex_lock(&olddev->ibi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (olddev->ibi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ibireq.handler = olddev->ibi->handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ibireq.max_payload_len = olddev->ibi->max_payload_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ibireq.num_slots = olddev->ibi->num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (olddev->ibi->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) enable_ibi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) i3c_dev_disable_ibi_locked(olddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) i3c_dev_free_ibi_locked(olddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) mutex_unlock(&olddev->ibi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) old_dyn_addr = olddev->info.dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) i3c_master_detach_i3c_dev(olddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) i3c_master_free_i3c_dev(olddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret = i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) goto err_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) * Depending on our previous state, the expected dynamic address might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) * differ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) * - if the device already had a dynamic address assigned, let's try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) * re-apply this one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * - if the device did not have a dynamic address and the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * requested a specific address, pick this one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) * - in any other case, keep the address automatically assigned by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) * master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (old_dyn_addr && old_dyn_addr != newdev->info.dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) expected_dyn_addr = old_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) else if (newdev->boardinfo && newdev->boardinfo->init_dyn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) expected_dyn_addr = newdev->boardinfo->init_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) expected_dyn_addr = newdev->info.dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (newdev->info.dyn_addr != expected_dyn_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) * Try to apply the expected dynamic address. If it fails, keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) * the address assigned by the master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ret = i3c_master_setnewda_locked(master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) newdev->info.dyn_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) expected_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) old_dyn_addr = newdev->info.dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) newdev->info.dyn_addr = expected_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) i3c_master_reattach_i3c_dev(newdev, old_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) dev_err(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) "Failed to assign reserved/old address to device %d%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) master->bus.id, newdev->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * Now is time to try to restore the IBI setup. If we're lucky,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * everything works as before, otherwise, all we can do is complain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * FIXME: maybe we should add callback to inform the driver that it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * should request the IBI again instead of trying to hide that from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) * him.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (ibireq.handler) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) mutex_lock(&newdev->ibi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = i3c_dev_request_ibi_locked(newdev, &ibireq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) dev_err(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "Failed to request IBI on device %d-%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) master->bus.id, newdev->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) } else if (enable_ibi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret = i3c_dev_enable_ibi_locked(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) dev_err(&master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "Failed to re-enable IBI on device %d-%llx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) master->bus.id, newdev->info.pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) mutex_unlock(&newdev->ibi_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) err_detach_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (newdev->dev && newdev->dev->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) newdev->dev->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) i3c_master_detach_i3c_dev(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) err_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) i3c_master_free_i3c_dev(newdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define OF_I3C_REG1_IS_I2C_DEV BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct device_node *node, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct i2c_dev_boardinfo *boardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct device *dev = &master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (!boardinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ret = of_i2c_get_board_info(dev, node, &boardinfo->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * The I3C Specification does not clearly say I2C devices with 10-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * address are supported. These devices can't be passed properly through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * DEFSLVS command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (boardinfo->base.flags & I2C_CLIENT_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) dev_err(dev, "I2C device with 10 bit address not supported.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* LVR is encoded in reg[2]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) boardinfo->lvr = reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) list_add_tail(&boardinfo->node, &master->boardinfo.i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) of_node_get(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) struct device_node *node, u32 *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct i3c_dev_boardinfo *boardinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct device *dev = &master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) enum i3c_addr_slot_status addrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) u32 init_dyn_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) boardinfo = devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (!boardinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) if (reg[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (reg[0] > I3C_MAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) if (addrstatus != I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) boardinfo->static_addr = reg[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (init_dyn_addr > I3C_MAX_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) addrstatus = i3c_bus_get_addr_slot_status(&master->bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) init_dyn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (addrstatus != I3C_ADDR_SLOT_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) boardinfo->pid = ((u64)reg[1] << 32) | reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if ((boardinfo->pid & GENMASK_ULL(63, 48)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) I3C_PID_RND_LOWER_32BITS(boardinfo->pid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) boardinfo->init_dyn_addr = init_dyn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) boardinfo->of_node = of_node_get(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) list_add_tail(&boardinfo->node, &master->boardinfo.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static int of_i3c_master_add_dev(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) u32 reg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) if (!master || !node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ret = of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) * The manufacturer ID can't be 0. If reg[1] == 0 that means we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) * dealing with an I2C device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (!reg[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ret = of_i3c_master_add_i2c_boardinfo(master, node, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ret = of_i3c_master_add_i3c_boardinfo(master, node, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static int of_populate_i3c_bus(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) struct device *dev = &master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) struct device_node *i3cbus_np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) if (!i3cbus_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) for_each_available_child_of_node(i3cbus_np, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ret = of_i3c_master_add_dev(master, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) * The user might want to limit I2C and I3C speed in case some devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) * on the bus are not supporting typical rates, or if the bus topology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) * prevents it from using max possible rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) master->bus.scl_rate.i2c = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) master->bus.scl_rate.i3c = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static int i3c_master_i2c_adapter_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct i2c_msg *xfers, int nxfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct i3c_master_controller *master = i2c_adapter_to_i3c_master(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct i2c_dev_desc *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (!xfers || !master || nxfers <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (!master->ops->i2c_xfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* Doing transfers to different devices is not supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) addr = xfers[0].addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) for (i = 1; i < nxfers; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (addr != xfers[i].addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) i3c_bus_normaluse_lock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) dev = i3c_master_find_i2c_dev_by_addr(master, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ret = master->ops->i2c_xfers(dev, xfers, nxfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) i3c_bus_normaluse_unlock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) return ret ? ret : nxfers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static u32 i3c_master_i2c_funcs(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static const struct i2c_algorithm i3c_master_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .master_xfer = i3c_master_i2c_adapter_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .functionality = i3c_master_i2c_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static int i3c_master_i2c_adapter_init(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) struct i2c_adapter *adap = i3c_master_to_i2c_adapter(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) struct i2c_dev_desc *i2cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) adap->dev.parent = master->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) adap->owner = master->dev.parent->driver->owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) adap->algo = &i3c_master_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) strncpy(adap->name, dev_name(master->dev.parent), sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* FIXME: Should we allow i3c masters to override these values? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) adap->timeout = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) * We silently ignore failures here. The bus should keep working
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) * correctly even if one or more i2c devices are not registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) i2cdev->dev = i2c_new_client_device(adap, &i2cdev->boardinfo->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static void i3c_master_i2c_adapter_cleanup(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) struct i2c_dev_desc *i2cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) i2c_del_adapter(&master->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) i3c_bus_for_each_i2cdev(&master->bus, i2cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) i2cdev->dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static void i3c_master_unregister_i3c_devs(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) struct i3c_dev_desc *i3cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) i3c_bus_for_each_i3cdev(&master->bus, i3cdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (!i3cdev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) i3cdev->dev->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (device_is_registered(&i3cdev->dev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) device_unregister(&i3cdev->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) put_device(&i3cdev->dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) i3cdev->dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) * i3c_master_queue_ibi() - Queue an IBI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) * @dev: the device this IBI is coming from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) * @slot: the IBI slot used to store the payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) * Queue an IBI to the controller workqueue. The IBI handler attached to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) * the dev will be called from a workqueue context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) atomic_inc(&dev->ibi->pending_ibis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) queue_work(dev->common.master->wq, &slot->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) EXPORT_SYMBOL_GPL(i3c_master_queue_ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static void i3c_master_handle_ibi(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct i3c_ibi_slot *slot = container_of(work, struct i3c_ibi_slot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) struct i3c_dev_desc *dev = slot->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct i3c_ibi_payload payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) payload.data = slot->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) payload.len = slot->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (dev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) dev->ibi->handler(dev->dev, &payload);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) master->ops->recycle_ibi_slot(dev, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (atomic_dec_and_test(&dev->ibi->pending_ibis))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) complete(&dev->ibi->all_ibis_handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static void i3c_master_init_ibi_slot(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct i3c_ibi_slot *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) slot->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) INIT_WORK(&slot->work, i3c_master_handle_ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct i3c_generic_ibi_slot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct i3c_ibi_slot base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) struct i3c_generic_ibi_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) unsigned int num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) struct i3c_generic_ibi_slot *slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) void *payload_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) struct list_head free_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) struct list_head pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) * i3c_generic_ibi_free_pool() - Free a generic IBI pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) * @pool: the IBI pool to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) * Free all IBI slots allated by a generic IBI pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) struct i3c_generic_ibi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) unsigned int nslots = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) while (!list_empty(&pool->free_slots)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) slot = list_first_entry(&pool->free_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) struct i3c_generic_ibi_slot, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) list_del(&slot->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) nslots++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) * If the number of freed slots is not equal to the number of allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) * slots we have a leak somewhere.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) WARN_ON(nslots != pool->num_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) kfree(pool->payload_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) kfree(pool->slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) kfree(pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) EXPORT_SYMBOL_GPL(i3c_generic_ibi_free_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) * i3c_generic_ibi_alloc_pool() - Create a generic IBI pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) * @dev: the device this pool will be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) * @req: IBI setup request describing what the device driver expects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) * Create a generic IBI pool based on the information provided in @req.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) * Return: a valid IBI pool in case of success, an ERR_PTR() otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) struct i3c_generic_ibi_pool *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) const struct i3c_ibi_setup *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct i3c_generic_ibi_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct i3c_generic_ibi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) pool = kzalloc(sizeof(*pool), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (!pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) spin_lock_init(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) INIT_LIST_HEAD(&pool->free_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) INIT_LIST_HEAD(&pool->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) pool->slots = kcalloc(req->num_slots, sizeof(*slot), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (!pool->slots) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) goto err_free_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (req->max_payload_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pool->payload_buf = kcalloc(req->num_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) req->max_payload_len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (!pool->payload_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) goto err_free_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) for (i = 0; i < req->num_slots; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) slot = &pool->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) i3c_master_init_ibi_slot(dev, &slot->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) if (req->max_payload_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) slot->base.data = pool->payload_buf +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) (i * req->max_payload_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) list_add_tail(&slot->node, &pool->free_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) pool->num_slots++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) return pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) err_free_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) i3c_generic_ibi_free_pool(pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) EXPORT_SYMBOL_GPL(i3c_generic_ibi_alloc_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * i3c_generic_ibi_get_free_slot() - Get a free slot from a generic IBI pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) * @pool: the pool to query an IBI slot on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) * Search for a free slot in a generic IBI pool.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) * The slot should be returned to the pool using i3c_generic_ibi_recycle_slot()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) * when it's no longer needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) * Return: a pointer to a free slot, or NULL if there's no free slot available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) struct i3c_ibi_slot *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) struct i3c_generic_ibi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) spin_lock_irqsave(&pool->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) slot = list_first_entry_or_null(&pool->free_slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) struct i3c_generic_ibi_slot, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) if (slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) list_del(&slot->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) spin_unlock_irqrestore(&pool->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return slot ? &slot->base : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) EXPORT_SYMBOL_GPL(i3c_generic_ibi_get_free_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) * i3c_generic_ibi_recycle_slot() - Return a slot to a generic IBI pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) * @pool: the pool to return the IBI slot to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) * @s: IBI slot to recycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) * Add an IBI slot back to its generic IBI pool. Should be called from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) * master driver struct_master_controller_ops->recycle_ibi() method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) struct i3c_ibi_slot *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) struct i3c_generic_ibi_slot *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) slot = container_of(s, struct i3c_generic_ibi_slot, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) spin_lock_irqsave(&pool->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) list_add_tail(&slot->node, &pool->free_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) spin_unlock_irqrestore(&pool->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) EXPORT_SYMBOL_GPL(i3c_generic_ibi_recycle_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static int i3c_master_check_ops(const struct i3c_master_controller_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (!ops || !ops->bus_init || !ops->priv_xfers ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) !ops->send_ccc_cmd || !ops->do_daa || !ops->i2c_xfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ops->request_ibi &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) (!ops->enable_ibi || !ops->disable_ibi || !ops->free_ibi ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) !ops->recycle_ibi_slot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * i3c_master_register() - register an I3C master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * @parent: the parent device (the one that provides this I3C master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * @ops: the master controller operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) * @secondary: true if you are registering a secondary master. Will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * -ENOTSUPP if set to true since secondary masters are not yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) * This function takes care of everything for you:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * - creates and initializes the I3C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) * - populates the bus with static I2C devs if @parent->of_node is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) * NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) * - registers all I3C devices added by the controller during bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) * initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) * - registers the I2C adapter and all I2C devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * Return: 0 in case of success, a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) int i3c_master_register(struct i3c_master_controller *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) const struct i3c_master_controller_ops *ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) bool secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) unsigned long i2c_scl_rate = I3C_BUS_I2C_FM_PLUS_SCL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) struct i3c_bus *i3cbus = i3c_master_get_bus(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) struct i2c_dev_boardinfo *i2cbi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) /* We do not support secondary masters yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) if (secondary)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ret = i3c_master_check_ops(ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) master->dev.parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) master->dev.of_node = of_node_get(parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) master->dev.bus = &i3c_bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) master->dev.type = &i3c_masterdev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) master->dev.release = i3c_masterdev_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) master->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) master->secondary = secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) INIT_LIST_HEAD(&master->boardinfo.i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) INIT_LIST_HEAD(&master->boardinfo.i3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ret = i3c_bus_init(i3cbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) device_initialize(&master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) dev_set_name(&master->dev, "i3c-%d", i3cbus->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ret = of_populate_i3c_bus(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) list_for_each_entry(i2cbi, &master->boardinfo.i2c, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) switch (i2cbi->lvr & I3C_LVR_I2C_INDEX_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) case I3C_LVR_I2C_INDEX(0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) if (mode < I3C_BUS_MODE_MIXED_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) mode = I3C_BUS_MODE_MIXED_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) case I3C_LVR_I2C_INDEX(1):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (mode < I3C_BUS_MODE_MIXED_LIMITED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) mode = I3C_BUS_MODE_MIXED_LIMITED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) case I3C_LVR_I2C_INDEX(2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (mode < I3C_BUS_MODE_MIXED_SLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) mode = I3C_BUS_MODE_MIXED_SLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) if (i2cbi->lvr & I3C_LVR_I2C_FM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) i2c_scl_rate = I3C_BUS_I2C_FM_SCL_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ret = i3c_bus_set_mode(i3cbus, mode, i2c_scl_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) master->wq = alloc_workqueue("%s", 0, 0, dev_name(parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (!master->wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ret = i3c_master_bus_init(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) goto err_put_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ret = device_add(&master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) goto err_cleanup_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) * Expose our I3C bus as an I2C adapter so that I2C devices are exposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) * through the I2C subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ret = i3c_master_i2c_adapter_init(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) goto err_del_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) * We're done initializing the bus and the controller, we can now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) * register I3C devices discovered during the initial DAA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) master->init_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) i3c_bus_normaluse_lock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) i3c_master_register_new_i3c_devs(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) i3c_bus_normaluse_unlock(&master->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) err_del_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) device_del(&master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) err_cleanup_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) i3c_master_bus_cleanup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) err_put_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) put_device(&master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) EXPORT_SYMBOL_GPL(i3c_master_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) * i3c_master_unregister() - unregister an I3C master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) * @master: master used to send frames on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) * Basically undo everything done in i3c_master_register().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) * Return: 0 in case of success, a negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) int i3c_master_unregister(struct i3c_master_controller *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) i3c_master_i2c_adapter_cleanup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) i3c_master_unregister_i3c_devs(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) i3c_master_bus_cleanup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) device_unregister(&master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) EXPORT_SYMBOL_GPL(i3c_master_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) int i3c_dev_do_priv_xfers_locked(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) struct i3c_priv_xfer *xfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) int nxfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) struct i3c_master_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) if (!master || !xfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (!master->ops->priv_xfers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) return master->ops->priv_xfers(dev, xfers, nxfers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) int i3c_dev_disable_ibi_locked(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) struct i3c_master_controller *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) if (!dev->ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) ret = master->ops->disable_ibi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) reinit_completion(&dev->ibi->all_ibis_handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) if (atomic_read(&dev->ibi->pending_ibis))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) wait_for_completion(&dev->ibi->all_ibis_handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) dev->ibi->enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) int i3c_dev_enable_ibi_locked(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (!dev->ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) ret = master->ops->enable_ibi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) dev->ibi->enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) int i3c_dev_request_ibi_locked(struct i3c_dev_desc *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) const struct i3c_ibi_setup *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) struct i3c_device_ibi_info *ibi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) if (!master->ops->request_ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) if (dev->ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) ibi = kzalloc(sizeof(*ibi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (!ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) atomic_set(&ibi->pending_ibis, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) init_completion(&ibi->all_ibis_handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) ibi->handler = req->handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ibi->max_payload_len = req->max_payload_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) ibi->num_slots = req->num_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) dev->ibi = ibi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) ret = master->ops->request_ibi(dev, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) kfree(ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) dev->ibi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) void i3c_dev_free_ibi_locked(struct i3c_dev_desc *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) struct i3c_master_controller *master = i3c_dev_get_master(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) if (!dev->ibi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (WARN_ON(dev->ibi->enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) WARN_ON(i3c_dev_disable_ibi_locked(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) master->ops->free_ibi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) kfree(dev->ibi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) dev->ibi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static int __init i3c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return bus_register(&i3c_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) subsys_initcall(i3c_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) static void __exit i3c_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) idr_destroy(&i3c_bus_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) bus_unregister(&i3c_bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) module_exit(i3c_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) MODULE_DESCRIPTION("I3C core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags