Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * I2C multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This module supports the PCA954x and PCA984x series of I2C multiplexer/switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * chips made by NXP Semiconductors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * This includes the:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	 PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *	 PCA9548, PCA9846, PCA9847, PCA9848 and PCA9849.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * These chips are all controlled via the I2C bus itself, and all have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * single 8-bit register. The upstream "parent" bus fans out to two,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * four, or eight downstream busses or channels; which of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * are selected is determined by the chip type and register contents. A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * mux can select only one sub-bus at a time; a switch can select any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * combination simultaneously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *	pca954x.c from Kumar Gala <galak@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Copyright (C) 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	pca954x.c from Ken Harrenstien
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Copyright (C) 2004 Google, Inc. (Ken Harrenstien)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	i2c-virtual_cb.c from Brian Kuschak <bkuschak@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *	pca9540.c from Jean Delvare <jdelvare@suse.de>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/i2c-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #include <dt-bindings/mux/mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCA954X_MAX_NCHANS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCA954X_IRQ_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) enum pca_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	pca_9540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	pca_9542,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	pca_9543,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	pca_9544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	pca_9545,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	pca_9546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	pca_9547,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pca_9548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	pca_9846,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	pca_9847,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pca_9848,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	pca_9849,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct chip_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u8 nchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 enable;	/* used for muxes only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u8 has_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	enum muxtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		pca954x_ismux = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		pca954x_isswi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	} muxtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct i2c_device_identity id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) struct pca954x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	const struct chip_desc *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u8 last_chan;		/* last register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* MUX_IDLE_AS_IS, MUX_IDLE_DISCONNECT or >= 0 for channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	s32 idle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct irq_domain *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned int irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Provide specs for the PCA954x types we know about */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static const struct chip_desc chips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[pca_9540] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.nchans = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.enable = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[pca_9542] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.nchans = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.enable = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.has_irq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[pca_9543] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.nchans = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.has_irq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[pca_9544] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.nchans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.enable = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.has_irq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	[pca_9545] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.nchans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.has_irq = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	[pca_9546] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.nchans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[pca_9547] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.nchans = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.enable = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[pca_9548] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.nchans = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.id = { .manufacturer_id = I2C_DEVICE_ID_NONE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	[pca_9846] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.nchans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			.manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			.part_id = 0x10b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	[pca_9847] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.nchans = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.enable = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			.manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			.part_id = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	[pca_9848] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.nchans = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.muxtype = pca954x_isswi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			.manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			.part_id = 0x10a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	[pca_9849] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.nchans = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.enable = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.muxtype = pca954x_ismux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.id = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			.manufacturer_id = I2C_DEVICE_ID_NXP_SEMICONDUCTORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			.part_id = 0x109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct i2c_device_id pca954x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{ "pca9540", pca_9540 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	{ "pca9542", pca_9542 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ "pca9543", pca_9543 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	{ "pca9544", pca_9544 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ "pca9545", pca_9545 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ "pca9546", pca_9546 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	{ "pca9547", pca_9547 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ "pca9548", pca_9548 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{ "pca9846", pca_9846 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ "pca9847", pca_9847 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ "pca9848", pca_9848 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ "pca9849", pca_9849 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_DEVICE_TABLE(i2c, pca954x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct of_device_id pca954x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ .compatible = "nxp,pca9540", .data = &chips[pca_9540] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ .compatible = "nxp,pca9542", .data = &chips[pca_9542] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ .compatible = "nxp,pca9543", .data = &chips[pca_9543] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ .compatible = "nxp,pca9544", .data = &chips[pca_9544] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ .compatible = "nxp,pca9545", .data = &chips[pca_9545] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ .compatible = "nxp,pca9546", .data = &chips[pca_9546] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ .compatible = "nxp,pca9547", .data = &chips[pca_9547] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ .compatible = "nxp,pca9548", .data = &chips[pca_9548] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ .compatible = "nxp,pca9846", .data = &chips[pca_9846] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ .compatible = "nxp,pca9847", .data = &chips[pca_9847] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ .compatible = "nxp,pca9848", .data = &chips[pca_9848] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ .compatible = "nxp,pca9849", .data = &chips[pca_9849] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DEVICE_TABLE(of, pca954x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)    for this as they will try to lock adapter a second time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int pca954x_reg_write(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			     struct i2c_client *client, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	union i2c_smbus_data dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return __i2c_smbus_xfer(adap, client->addr, client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 				I2C_SMBUS_WRITE, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				I2C_SMBUS_BYTE, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static u8 pca954x_regval(struct pca954x *data, u8 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* We make switches look like muxes, not sure how to be smarter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (data->chip->muxtype == pca954x_ismux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return chan | data->chip->enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		return 1 << chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	u8 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	regval = pca954x_regval(data, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Only select the channel if its different from the last channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (data->last_chan != regval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		ret = pca954x_reg_write(muxc->parent, client, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		data->last_chan = ret < 0 ? 0 : regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	s32 idle_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	idle_state = READ_ONCE(data->idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (idle_state >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		/* Set the mux back to a predetermined channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return pca954x_select_chan(muxc, idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (idle_state == MUX_IDLE_DISCONNECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		/* Deselect active channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		data->last_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return pca954x_reg_write(muxc->parent, client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 					 data->last_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* otherwise leave as-is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static ssize_t idle_state_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				    struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				    char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return sprintf(buf, "%d\n", READ_ONCE(data->idle_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static ssize_t idle_state_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	ret = kstrtoint(buf, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	    (val < 0 || val >= data->chip->nchans))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	i2c_lock_bus(muxc->parent, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	WRITE_ONCE(data->idle_state, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	 * Set the mux into a state consistent with the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 * idle_state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (data->last_chan || val != MUX_IDLE_DISCONNECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		ret = pca954x_deselect_mux(muxc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	i2c_unlock_bus(muxc->parent, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return ret < 0 ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static DEVICE_ATTR_RW(idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static irqreturn_t pca954x_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct pca954x *data = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	ret = i2c_smbus_read_byte(data->client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	pending = (ret >> PCA954X_IRQ_OFFSET) & (BIT(data->chip->nchans) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	for_each_set_bit(i, &pending, data->chip->nchans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		handle_nested_irq(irq_linear_revmap(data->irq, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return IRQ_RETVAL(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct irq_chip pca954x_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.name = "i2c-mux-pca954x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.irq_set_type = pca954x_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int pca954x_irq_setup(struct i2c_mux_core *muxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int c, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!data->chip->has_irq || client->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	raw_spin_lock_init(&data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	data->irq = irq_domain_add_linear(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 					  data->chip->nchans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 					  &irq_domain_simple_ops, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (!data->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	for (c = 0; c < data->chip->nchans; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		irq = irq_create_mapping(data->irq, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			dev_err(&client->dev, "failed irq create map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		irq_set_chip_data(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		irq_set_chip_and_handler(irq, &pca954x_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void pca954x_cleanup(struct i2c_mux_core *muxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	int c, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		for (c = 0; c < data->chip->nchans; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			irq = irq_find_mapping(data->irq, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			irq_dispose_mapping(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		irq_domain_remove(data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	i2c_mux_del_adapters(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int pca954x_init(struct i2c_client *client, struct pca954x *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (data->idle_state >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		data->last_chan = pca954x_regval(data, data->idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		data->last_chan = 0; /* Disconnect multiplexer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	ret = i2c_smbus_write_byte(client, data->last_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		data->last_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)  * I2C init/probing/exit functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int pca954x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct pca954x *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	muxc = i2c_mux_alloc(adap, dev, PCA954X_MAX_NCHANS, sizeof(*data), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			     pca954x_select_chan, pca954x_deselect_mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (!muxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	i2c_set_clientdata(client, muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	/* Reset the mux if a reset GPIO is specified. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		gpiod_set_value_cansleep(gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		/* Give the chip some time to recover. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	data->chip = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (!data->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		data->chip = &chips[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (data->chip->id.manufacturer_id != I2C_DEVICE_ID_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		struct i2c_device_identity id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		ret = i2c_get_device_id(client, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		if (ret && ret != -EOPNOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		if (!ret &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		    (id.manufacturer_id != data->chip->id.manufacturer_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		     id.part_id != data->chip->id.part_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 			dev_warn(dev, "unexpected device id %03x-%03x-%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				 id.manufacturer_id, id.part_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 				 id.die_revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	data->idle_state = MUX_IDLE_AS_IS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (device_property_read_u32(dev, "idle-state", &data->idle_state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		if (device_property_read_bool(dev, "i2c-mux-idle-disconnect"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 			data->idle_state = MUX_IDLE_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	 * Write the mux register at addr to verify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	 * that the mux is in fact present. This also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	 * initializes the mux to a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	 * or disconnected state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ret = pca954x_init(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		dev_warn(dev, "probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	ret = pca954x_irq_setup(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		goto fail_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	/* Now create an adapter for each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	for (num = 0; num < data->chip->nchans; num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		ret = i2c_mux_add_adapter(muxc, 0, num, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 			goto fail_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	if (data->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		ret = devm_request_threaded_irq(dev, data->client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 						NULL, pca954x_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 						IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 						"pca954x", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 			goto fail_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	 * The attr probably isn't going to be needed in most cases,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	 * so don't fail completely on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	device_create_file(dev, &dev_attr_idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	dev_info(dev, "registered %d multiplexed busses for I2C %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		 num, data->chip->muxtype == pca954x_ismux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 				? "mux" : "switch", client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) fail_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	pca954x_cleanup(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static int pca954x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	device_remove_file(&client->dev, &dev_attr_idle_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	pca954x_cleanup(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int pca954x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	struct pca954x *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	ret = pca954x_init(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		dev_err(&client->dev, "failed to verify mux presence\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static SIMPLE_DEV_PM_OPS(pca954x_pm, NULL, pca954x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct i2c_driver pca954x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		.name	= "pca954x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		.pm	= &pca954x_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 		.of_match_table = pca954x_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	.probe		= pca954x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	.remove		= pca954x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	.id_table	= pca954x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) module_i2c_driver(pca954x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MODULE_AUTHOR("Rodolfo Giometti <giometti@linux.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_DESCRIPTION("PCA954x I2C mux/switch driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_LICENSE("GPL v2");