^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * I2C multiplexer driver for PCA9541 bus master selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2010 Ericsson AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Guenter Roeck <linux@roeck-us.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Derived from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * pca954x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/i2c-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The PCA9541 is a bus master selector. It supports two I2C masters connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * to a single slave bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Before each bus transaction, a master has to acquire bus ownership. After the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * transaction is complete, bus ownership has to be released. This fits well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * into the I2C multiplexer framework, which provides select and release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * functions for this purpose. For this reason, this driver is modeled as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * single-channel I2C bus multiplexer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * This driver assumes that the two bus masters are controlled by two different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * hosts. If a single host controls both masters, platform code has to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * that only one of the masters is instantiated at any given time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCA9541_CONTROL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCA9541_ISTAT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCA9541_CTL_MYBUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCA9541_CTL_NMYBUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCA9541_CTL_BUSON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCA9541_CTL_NBUSON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCA9541_CTL_BUSINIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCA9541_CTL_TESTON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCA9541_CTL_NTESTON BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCA9541_ISTAT_INTIN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCA9541_ISTAT_BUSINIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCA9541_ISTAT_BUSOK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCA9541_ISTAT_BUSLOST BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCA9541_ISTAT_MYTEST BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCA9541_ISTAT_NMYTEST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define mybus(x) (!((x) & MYBUS) || ((x) & MYBUS) == MYBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define busoff(x) (!((x) & BUSON) || ((x) & BUSON) == BUSON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* arbitration timeouts, in jiffies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ARB_TIMEOUT (HZ / 8) /* 125 ms until forcing bus ownership */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ARB2_TIMEOUT (HZ / 4) /* 250 ms until acquisition failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* arbitration retry delays, in us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SELECT_DELAY_SHORT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SELECT_DELAY_LONG 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct pca9541 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long select_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long arb_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct i2c_device_id pca9541_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {"pca9541", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_DEVICE_TABLE(i2c, pca9541_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct of_device_id pca9541_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .compatible = "nxp,pca9541" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_DEVICE_TABLE(of, pca9541_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Write to chip register. Don't use i2c_transfer()/i2c_smbus_xfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * as they will try to lock the adapter a second time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) union i2c_smbus_data data = { .byte = val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return __i2c_smbus_xfer(adap, client->addr, client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) I2C_SMBUS_WRITE, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) I2C_SMBUS_BYTE_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Read from chip register. Don't use i2c_transfer()/i2c_smbus_xfer()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * as they will try to lock adapter a second time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int pca9541_reg_read(struct i2c_client *client, u8 command)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) union i2c_smbus_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = __i2c_smbus_xfer(adap, client->addr, client->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) I2C_SMBUS_READ, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) I2C_SMBUS_BYTE_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret ?: data.byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Arbitration management functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Release bus. Also reset NTESTON and BUSINIT if it was set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void pca9541_release_bus(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg = pca9541_reg_read(client, PCA9541_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (reg >= 0 && !busoff(reg) && mybus(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pca9541_reg_write(client, PCA9541_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (reg & PCA9541_CTL_NBUSON) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Arbitration is defined as a two-step process. A bus master can only activate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * the slave bus if it owns it; otherwise it has to request ownership first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * This multi-step process ensures that access contention is resolved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * gracefully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Bus Ownership Other master Action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * state requested access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * ----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * off - yes wait for arbitration timeout or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * for other master to drop request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * off no no take ownership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * off yes no turn on bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * on yes - done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * on no - wait for arbitration timeout or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * for other master to release bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The main contention point occurs if the slave bus is off and both masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * request ownership at the same time. In this case, one master will turn on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * the slave bus, believing that it owns it. The other master will request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * bus ownership. Result is that the bus is turned on, and master which did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * _not_ own the slave bus before ends up owning it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Control commands per PCA9541 datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const u8 pca9541_control[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Channel arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Return values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * <0: error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * 0 : bus not acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * 1 : bus acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int pca9541_arbitrate(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pca9541 *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) reg = pca9541_reg_read(client, PCA9541_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (busoff(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int istat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Bus is off. Request ownership or turn it on unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * other master requested ownership.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) istat = pca9541_reg_read(client, PCA9541_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!(istat & PCA9541_ISTAT_NMYTEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) || time_is_before_eq_jiffies(data->arb_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Other master did not request ownership,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * or arbitration timeout expired. Take the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pca9541_reg_write(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PCA9541_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pca9541_control[reg & 0x0f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) | PCA9541_CTL_NTESTON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data->select_timeout = SELECT_DELAY_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Other master requested ownership.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Set extra long timeout to give it time to acquire it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) data->select_timeout = SELECT_DELAY_LONG * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else if (mybus(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Bus is on, and we own it. We are done with acquisition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Reset NTESTON and BUSINIT, then return success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pca9541_reg_write(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PCA9541_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg & ~(PCA9541_CTL_NTESTON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) | PCA9541_CTL_BUSINIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Other master owns the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * If arbitration timeout has expired, force ownership.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Otherwise request it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) data->select_timeout = SELECT_DELAY_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (time_is_before_eq_jiffies(data->arb_timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Time is up, take the bus and reset it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pca9541_reg_write(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PCA9541_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pca9541_control[reg & 0x0f]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) | PCA9541_CTL_BUSINIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) | PCA9541_CTL_NTESTON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Request bus ownership if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!(reg & PCA9541_CTL_NTESTON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pca9541_reg_write(client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PCA9541_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg | PCA9541_CTL_NTESTON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int pca9541_select_chan(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct pca9541 *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long timeout = jiffies + ARB2_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* give up after this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) data->arb_timeout = jiffies + ARB_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* force bus ownership after this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = pca9541_arbitrate(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret < 0 ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (data->select_timeout == SELECT_DELAY_SHORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) udelay(data->select_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) msleep(data->select_timeout / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } while (time_is_after_eq_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int pca9541_release_chan(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pca9541 *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct i2c_client *client = data->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pca9541_release_bus(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * I2C init/probing/exit functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int pca9541_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct pca9541 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * I2C accesses are unprotected here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * We have to lock the I2C segment before releasing the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) i2c_lock_bus(adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pca9541_release_bus(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) i2c_unlock_bus(adap, I2C_LOCK_SEGMENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Create mux adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) I2C_MUX_ARBITRATOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pca9541_select_chan, pca9541_release_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!muxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) i2c_set_clientdata(client, muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ret = i2c_mux_add_adapter(muxc, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_info(&client->dev, "registered master selector for I2C %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int pca9541_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i2c_mux_del_adapters(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct i2c_driver pca9541_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .name = "pca9541",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .of_match_table = of_match_ptr(pca9541_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .probe = pca9541_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .remove = pca9541_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .id_table = pca9541_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) module_i2c_driver(pca9541_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_DESCRIPTION("PCA9541 I2C master selector driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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