Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Linear Technology LTC4306 and LTC4305 I2C multiplexer/switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on: i2c-mux-pca954x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Datasheet: http://cds.linear.com/docs/en/datasheet/4306.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c-mux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LTC4305_MAX_NCHANS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LTC4306_MAX_NCHANS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LTC_REG_STATUS	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LTC_REG_CONFIG	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LTC_REG_MODE	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LTC_REG_SWITCH	0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LTC_DOWNSTREAM_ACCL_EN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LTC_UPSTREAM_ACCL_EN	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LTC_GPIO_ALL_INPUT	0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LTC_SWITCH_MASK		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) enum ltc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	ltc_4305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	ltc_4306,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct chip_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u8 nchans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u8 num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct ltc4306 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct gpio_chip gpiochip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	const struct chip_desc *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct chip_desc chips[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[ltc_4305] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.nchans = LTC4305_MAX_NCHANS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	[ltc_4306] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.nchans = LTC4306_MAX_NCHANS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.num_gpios = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static bool ltc4306_is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return (reg == LTC_REG_CONFIG) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static const struct regmap_config ltc4306_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.max_register = LTC_REG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.volatile_reg = ltc4306_is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.cache_type = REGCACHE_FLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int ltc4306_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ret = regmap_read(data->regmap, LTC_REG_CONFIG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return !!(val & BIT(1 - offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void ltc4306_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			     int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	regmap_update_bits(data->regmap, LTC_REG_CONFIG, BIT(5 - offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			   value ? BIT(5 - offset) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int ltc4306_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				      unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ret = regmap_read(data->regmap, LTC_REG_MODE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return !!(val & BIT(7 - offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int ltc4306_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return regmap_update_bits(data->regmap, LTC_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				  BIT(7 - offset), BIT(7 - offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int ltc4306_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 					 unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ltc4306_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return regmap_update_bits(data->regmap, LTC_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				  BIT(7 - offset), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int ltc4306_gpio_set_config(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				   unsigned int offset, unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct ltc4306 *data = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	switch (pinconf_to_config_param(config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		val = BIT(4 - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return regmap_update_bits(data->regmap, LTC_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				  BIT(4 - offset), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int ltc4306_gpio_init(struct ltc4306 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct device *dev = regmap_get_device(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!data->chip->num_gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	data->gpiochip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	data->gpiochip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	data->gpiochip.ngpio = data->chip->num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	data->gpiochip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	data->gpiochip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	data->gpiochip.get_direction = ltc4306_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	data->gpiochip.direction_input = ltc4306_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	data->gpiochip.direction_output = ltc4306_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	data->gpiochip.get = ltc4306_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	data->gpiochip.set = ltc4306_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	data->gpiochip.set_config = ltc4306_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	data->gpiochip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* gpiolib assumes all GPIOs default input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	regmap_write(data->regmap, LTC_REG_MODE, LTC_GPIO_ALL_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return devm_gpiochip_add_data(dev, &data->gpiochip, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int ltc4306_select_mux(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct ltc4306 *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return regmap_update_bits(data->regmap, LTC_REG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				  LTC_SWITCH_MASK, BIT(7 - chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int ltc4306_deselect_mux(struct i2c_mux_core *muxc, u32 chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct ltc4306 *data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return regmap_update_bits(data->regmap, LTC_REG_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				  LTC_SWITCH_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct i2c_device_id ltc4306_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ "ltc4305", ltc_4305 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ "ltc4306", ltc_4306 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DEVICE_TABLE(i2c, ltc4306_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct of_device_id ltc4306_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ .compatible = "lltc,ltc4305", .data = &chips[ltc_4305] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ .compatible = "lltc,ltc4306", .data = &chips[ltc_4306] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DEVICE_TABLE(of, ltc4306_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int ltc4306_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	const struct chip_desc *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct i2c_mux_core *muxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct ltc4306 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	bool idle_disc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	int num, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	chip = of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		chip = &chips[i2c_match_id(ltc4306_id, client)->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	idle_disc = device_property_read_bool(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					      "i2c-mux-idle-disconnect");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	muxc = i2c_mux_alloc(adap, &client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			     chip->nchans, sizeof(*data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			     I2C_MUX_LOCKED, ltc4306_select_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			     idle_disc ? ltc4306_deselect_mux : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (!muxc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	data = i2c_mux_priv(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	data->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	i2c_set_clientdata(client, muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	data->regmap = devm_regmap_init_i2c(client, &ltc4306_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ret = PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(&client->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* Reset and enable the mux if an enable GPIO is specified. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	gpio = devm_gpiod_get_optional(&client->dev, "enable", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (IS_ERR(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		gpiod_set_value(gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * Write the mux register at addr to verify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * that the mux is in fact present. This also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * initializes the mux to disconnected state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (regmap_write(data->regmap, LTC_REG_SWITCH, 0) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		dev_warn(&client->dev, "probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (device_property_read_bool(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				      "ltc,downstream-accelerators-enable"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		val |= LTC_DOWNSTREAM_ACCL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (device_property_read_bool(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				      "ltc,upstream-accelerators-enable"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		val |= LTC_UPSTREAM_ACCL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (regmap_write(data->regmap, LTC_REG_CONFIG, val) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = ltc4306_gpio_init(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* Now create an adapter for each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	for (num = 0; num < chip->nchans; num++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		ret = i2c_mux_add_adapter(muxc, 0, num, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			i2c_mux_del_adapters(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		 "registered %d multiplexed busses for I2C switch %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		 num, client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int ltc4306_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct i2c_mux_core *muxc = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	i2c_mux_del_adapters(muxc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static struct i2c_driver ltc4306_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.name	= "ltc4306",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.of_match_table = of_match_ptr(ltc4306_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.probe_new	= ltc4306_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.remove		= ltc4306_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.id_table	= ltc4306_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) module_i2c_driver(ltc4306_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_DESCRIPTION("Linear Technology LTC4306, LTC4305 I2C mux/switch driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_LICENSE("GPL v2");