^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) i2c-stub.c - I2C/SMBus chip emulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (c) 2004 Mark M. Hoffman <mhoffman@lightlink.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Copyright (C) 2007-2014 Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define pr_fmt(fmt) "i2c-stub: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_CHIPS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Support for I2C_FUNC_SMBUS_BLOCK_DATA is disabled by default and must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * be enabled explicitly by setting the I2C_FUNC_SMBUS_BLOCK_DATA bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * in the 'functionality' module parameter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STUB_FUNC_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) (I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) I2C_FUNC_SMBUS_I2C_BLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STUB_FUNC_ALL \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) (STUB_FUNC_DEFAULT | I2C_FUNC_SMBUS_BLOCK_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned short chip_addr[MAX_CHIPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param_array(chip_addr, ushort, NULL, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(chip_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "Chip addresses (up to 10, between 0x03 and 0x77)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static unsigned long functionality = STUB_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(functionality, ulong, S_IRUGO | S_IWUSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(functionality, "Override functionality bitfield");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Some chips have banked register ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static u8 bank_reg[MAX_CHIPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) module_param_array(bank_reg, byte, NULL, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_PARM_DESC(bank_reg, "Bank register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static u8 bank_mask[MAX_CHIPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param_array(bank_mask, byte, NULL, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_PARM_DESC(bank_mask, "Bank value mask");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u8 bank_start[MAX_CHIPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param_array(bank_start, byte, NULL, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(bank_start, "First banked register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static u8 bank_end[MAX_CHIPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_param_array(bank_end, byte, NULL, S_IRUGO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_PARM_DESC(bank_end, "Last banked register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct smbus_block_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 block[I2C_SMBUS_BLOCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct stub_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u16 words[256]; /* Byte operations use the LSB as per SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) specification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct list_head smbus_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* For chips with banks, extra registers are allocated dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 bank_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 bank_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 bank_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 bank_sel; /* Currently selected bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 bank_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 bank_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 bank_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 *bank_words; /* Room for bank_mask * bank_size registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct stub_chip *stub_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int stub_chips_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct smbus_block_data *stub_find_block(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct stub_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 command, bool create)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct smbus_block_data *b, *rb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) list_for_each_entry(b, &chip->smbus_blocks, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (b->command == command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rb = b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (rb == NULL && create) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rb = devm_kzalloc(dev, sizeof(*rb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (rb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rb->command = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) list_add(&rb->node, &chip->smbus_blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u16 *stub_get_wordp(struct stub_chip *chip, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (chip->bank_sel &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) offset >= chip->bank_start && offset <= chip->bank_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return chip->bank_words +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (chip->bank_sel - 1) * chip->bank_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) offset - chip->bank_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return chip->words + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Return negative errno on error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static s32 stub_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) char read_write, u8 command, int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) s32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct stub_chip *chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct smbus_block_data *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 *wordp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Search for the right chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < stub_chips_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (addr == chip_addr[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) chip = stub_chips + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_dbg(&adap->dev, "smbus quick - addr 0x%02x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) chip->pointer = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "smbus byte - addr 0x%02x, wrote 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) addr, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) wordp = stub_get_wordp(chip, chip->pointer++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) data->byte = *wordp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "smbus byte - addr 0x%02x, read 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) addr, data->byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) wordp = stub_get_wordp(chip, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *wordp &= 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *wordp |= data->byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "smbus byte data - addr 0x%02x, wrote 0x%02x at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) addr, data->byte, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Set the bank as needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (chip->bank_words && command == chip->bank_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) chip->bank_sel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) (data->byte >> chip->bank_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) & chip->bank_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "switching to bank %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) chip->bank_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) data->byte = *wordp & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "smbus byte data - addr 0x%02x, read 0x%02x at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) addr, data->byte, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) chip->pointer = command + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) wordp = stub_get_wordp(chip, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *wordp = data->word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "smbus word data - addr 0x%02x, wrote 0x%04x at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) addr, data->word, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data->word = *wordp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "smbus word data - addr 0x%02x, read 0x%04x at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) addr, data->word, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * We ignore banks here, because banked chips don't use I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * block transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (data->block[0] > 256 - command) /* Avoid overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data->block[0] = 256 - command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chip->words[command + i] &= 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) chip->words[command + i] |= data->block[1 + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "i2c block data - addr 0x%02x, wrote %d bytes at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) addr, len, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) data->block[1 + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) chip->words[command + i] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "i2c block data - addr 0x%02x, read %d bytes at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) addr, len, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * We ignore banks here, because chips typically don't use both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * banks and SMBus block transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) b = stub_find_block(&adap->dev, chip, command, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (b == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) b = stub_find_block(&adap->dev, chip, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (b == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Largest write sets read block length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (len > b->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) b->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) b->block[i] = data->block[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* update for byte and word commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) chip->words[command] = (b->block[0] << 8) | b->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "smbus block data - addr 0x%02x, wrote %d bytes at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) addr, len, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (b == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "SMBus block read command without prior block write not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) len = b->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) data->block[0] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) data->block[i + 1] = b->block[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "smbus block data - addr 0x%02x, read %d bytes at 0x%02x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) addr, len, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_dbg(&adap->dev, "Unsupported I2C/SMBus command\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } /* switch (size) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static u32 stub_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return STUB_FUNC_ALL & functionality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .functionality = stub_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .smbus_xfer = stub_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct i2c_adapter stub_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .algo = &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "SMBus stub driver",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int __init i2c_stub_allocate_banks(int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct stub_chip *chip = stub_chips + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) chip->bank_reg = bank_reg[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) chip->bank_start = bank_start[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) chip->bank_end = bank_end[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) chip->bank_size = bank_end[i] - bank_start[i] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* We assume that all bits in the mask are contiguous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) chip->bank_mask = bank_mask[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) while (!(chip->bank_mask & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chip->bank_shift++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) chip->bank_mask >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) chip->bank_words = kcalloc(chip->bank_mask * chip->bank_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sizeof(u16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!chip->bank_words)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_debug("Allocated %u banks of %u words each (registers 0x%02x to 0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) chip->bank_mask, chip->bank_size, chip->bank_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) chip->bank_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void i2c_stub_free(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (i = 0; i < stub_chips_nr; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) kfree(stub_chips[i].bank_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) kfree(stub_chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int __init i2c_stub_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!chip_addr[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_err("Please specify a chip address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) for (i = 0; i < MAX_CHIPS && chip_addr[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (chip_addr[i] < 0x03 || chip_addr[i] > 0x77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_err("Invalid chip address 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) chip_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_info("Virtual chip at 0x%02x\n", chip_addr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Allocate memory for all chips at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) stub_chips_nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) stub_chips = kcalloc(stub_chips_nr, sizeof(struct stub_chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!stub_chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (i = 0; i < stub_chips_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) INIT_LIST_HEAD(&stub_chips[i].smbus_blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Allocate extra memory for banked register ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (bank_mask[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = i2c_stub_allocate_banks(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) goto fail_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = i2c_add_adapter(&stub_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto fail_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) fail_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) i2c_stub_free();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void __exit i2c_stub_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i2c_del_adapter(&stub_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) i2c_stub_free();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_DESCRIPTION("I2C stub driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) module_init(i2c_stub_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) module_exit(i2c_stub_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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