^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Sanechips Technology Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Baoyou Xie <baoyou.xie@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define REG_CMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define REG_DEVADDR_H 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_DEVADDR_L 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define REG_CLK_DIV_FS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REG_CLK_DIV_HS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REG_WRCONF 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_RDCONF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_DATA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_STAT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_STOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_MASTER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_ADDR_MODE_TEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_IRQ_MSK_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_RW_READ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_CMB_RW_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_START BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_ADDR_LOW_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_ADDR_LOW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_ADDR_HI_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_ADDR_HI_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_WFIFO_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_RFIFO_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_IRQ_ACK_CLEAR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_INT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_TRANS_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_SR_EDEVICE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_SR_EDATA BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_FIFO_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_TIMEOUT msecs_to_jiffies(1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DEV(i2c) ((i2c)->adap.dev.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct zx2967_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) size_t residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int msg_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 *cur_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 access_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writel_relaxed(val, i2c->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return readl_relaxed(i2c->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void *data, unsigned long reg, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writesb(i2c->reg_base + reg, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void *data, unsigned long reg, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) readsb(i2c->reg_base + reg, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) status = zx2967_i2c_readl(i2c, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) status |= I2C_IRQ_ACK_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) zx2967_i2c_writel(i2c, status, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ctl = zx2967_i2c_readl(i2c, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (i2c->msg_rd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ctl |= I2C_RW_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ctl &= ~I2C_RW_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ctl &= ~I2C_CMB_RW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ctl |= I2C_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) zx2967_i2c_writel(i2c, ctl, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (i2c->msg_rd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) offset = REG_RDCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val = I2C_RFIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) offset = REG_WRCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = I2C_WFIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val |= zx2967_i2c_readl(i2c, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) zx2967_i2c_writel(i2c, val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 val[I2C_FIFO_MAX] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (size > I2C_FIFO_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) size, I2C_FIFO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) zx2967_i2c_readsb(i2c, val, REG_DATA, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *i2c->cur_trans++ = val[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) i2c->residue--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) size_t residue = i2c->residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 *buf = i2c->cur_trans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (residue == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(DEV(i2c), "residue is %d\n", (int)residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (residue <= I2C_FIFO_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Again update before writing to FIFO to make sure isr sees. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) i2c->residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) i2c->cur_trans = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) i2c->residue -= I2C_FIFO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) i2c->cur_trans += I2C_FIFO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) zx2967_i2c_writel(i2c, 1, REG_RDCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) zx2967_i2c_flush_fifos(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) status = zx2967_i2c_readl(i2c, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) status |= I2C_IRQ_ACK_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) zx2967_i2c_writel(i2c, status, REG_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) zx2967_i2c_isr_clr(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (status & I2C_SR_EDEVICE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) i2c->error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else if (status & I2C_SR_EDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) i2c->error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else if (status & I2C_TRANS_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) i2c->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) complete(&i2c->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int rd = i2c->msg_rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reinit_completion(&i2c->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (rd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = zx2967_i2c_fill_tx_fifo(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) zx2967_i2c_start_ctrl(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) time_left = wait_for_completion_timeout(&i2c->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (time_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (i2c->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return i2c->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) zx2967_i2c_flush_fifos(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) i2c->cur_trans = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) i2c->residue = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) i2c->access_cnt = msg->len / I2C_FIFO_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) i2c->msg_rd = msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < i2c->access_cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (i2c->residue > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) i2c->residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) i2c->access_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int zx2967_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) zx2967_set_addr(i2c, msgs->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) char read_write, u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val = zx2967_i2c_readl(i2c, REG_RDCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) val |= I2C_RFIFO_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) zx2967_i2c_writel(i2c, val, REG_RDCONF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) zx2967_set_addr(i2c, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) val = zx2967_i2c_readl(i2c, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val &= ~I2C_RW_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) zx2967_i2c_writel(i2c, command, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) zx2967_i2c_writel(i2c, command, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) zx2967_i2c_writel(i2c, data->byte, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) zx2967_i2c_writel(i2c, command, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) zx2967_i2c_writel(i2c, (data->word & 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reinit_completion(&i2c->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val = zx2967_i2c_readl(i2c, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) val |= I2C_CMB_RW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) val = zx2967_i2c_readl(i2c, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val |= I2C_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) time_left = wait_for_completion_timeout(&i2c->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (time_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (i2c->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return i2c->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) val = zx2967_i2c_readl(i2c, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) data->byte = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) data->word = (buf[0] << 8) | buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) reinit_completion(&i2c->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val = zx2967_i2c_readl(i2c, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= I2C_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) zx2967_i2c_writel(i2c, val, REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) time_left = wait_for_completion_timeout(&i2c->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (time_left == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (i2c->error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return i2c->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 command, int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (size == I2C_SMBUS_QUICK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) read_write = I2C_SMBUS_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) zx2967_smbus_xfer_prepare(i2c, addr, read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) command, size, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return zx2967_smbus_xfer_read(i2c, size, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return zx2967_smbus_xfer_write(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static u32 zx2967_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) I2C_FUNC_SMBUS_QUICK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) I2C_FUNC_SMBUS_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) I2C_FUNC_SMBUS_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct zx2967_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) i2c_mark_adapter_suspended(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int __maybe_unused zx2967_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct zx2967_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) i2c_mark_adapter_resumed(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) zx2967_i2c_suspend, zx2967_i2c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct i2c_algorithm zx2967_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .master_xfer = zx2967_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .smbus_xfer = zx2967_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .functionality = zx2967_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct of_device_id zx2967_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .compatible = "zte,zx296718-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int zx2967_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct zx2967_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(&pdev->dev, "missing controller clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_err(&pdev->dev, "failed to enable i2c_clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = device_property_read_u32(&pdev->dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &i2c->clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(&pdev->dev, "missing clock-frequency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) i2c->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) i2c->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i2c->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) init_completion(&i2c->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ret = zx2967_i2c_reset_hardware(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_err(&pdev->dev, "failed to initialize i2c controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = devm_request_irq(&pdev->dev, i2c->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) strlcpy(i2c->adap.name, "zx2967 i2c adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sizeof(i2c->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) i2c->adap.algo = &zx2967_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) i2c->adap.quirks = &zx2967_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) i2c->adap.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = i2c_add_numbered_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) goto err_clk_unprepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) err_clk_unprepare:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int zx2967_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static struct platform_driver zx2967_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .probe = zx2967_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .remove = zx2967_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "zx2967_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .of_match_table = zx2967_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .pm = &zx2967_i2c_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) module_platform_driver(zx2967_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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