^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright 2011, Netlogic Microsystems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* XLR I2C REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XLR_I2C_CFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XLR_I2C_CLKDIV 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XLR_I2C_DEVADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XLR_I2C_ADDR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XLR_I2C_DATAOUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XLR_I2C_DATAIN 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XLR_I2C_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XLR_I2C_STARTXFR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XLR_I2C_BYTECNT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XLR_I2C_HDSTATIM 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Sigma Designs additional registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XLR_I2C_INT_EN 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XLR_I2C_INT_STAT 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* XLR I2C REGISTERS FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define XLR_I2C_BUS_BUSY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XLR_I2C_SDOEMPTY 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XLR_I2C_RXRDY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XLR_I2C_ACK_ERR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XLR_I2C_ARB_STARTERR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Register Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XLR_I2C_CFG_ADDR 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XLR_I2C_CFG_NOADDR 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XLR_I2C_STARTXFR_ND 0x02 /* No Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XLR_I2C_STARTXFR_RD 0x01 /* Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XLR_I2C_STARTXFR_WR 0x00 /* Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XLR_I2C_TIMEOUT 10 /* timeout per byte in msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * On XLR/XLS, we need to use __raw_ IO to read the I2C registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * because they are in the big-endian MMIO area on the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * The readl/writel implementation on XLR/XLS byteswaps, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * those are for its little-endian PCI space (see arch/mips/Kconfig).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writel(val, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return __raw_readl(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XLR_I2C_FLAG_IRQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct xlr_i2c_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 flags; /* optional feature support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 status_busy; /* value of STATUS[0] when busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 cfg_extra; /* extra CFG bits to set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct xlr_i2c_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const struct xlr_i2c_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int xlr_i2c_busy(struct xlr_i2c_private *priv, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return (status & XLR_I2C_BUS_BUSY) == priv->cfg->status_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int xlr_i2c_idle(struct xlr_i2c_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return !xlr_i2c_busy(priv, xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int xlr_i2c_wait(struct xlr_i2c_private *priv, unsigned long timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) t = wait_event_timeout(priv->wait, xlr_i2c_idle(priv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) msecs_to_jiffies(timeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return status & XLR_I2C_ACK_ERR ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void xlr_i2c_tx_irq(struct xlr_i2c_private *priv, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (status & XLR_I2C_SDOEMPTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) msg->buf[priv->pos++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void xlr_i2c_rx_irq(struct xlr_i2c_private *priv, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (status & XLR_I2C_RXRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msg->buf[priv->pos++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static irqreturn_t xlr_i2c_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct xlr_i2c_private *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct i2c_msg *msg = priv->msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 int_stat, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int_stat = xlr_i2c_rdreg(priv->iobase, XLR_I2C_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!int_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, int_stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (priv->pos < msg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) xlr_i2c_rx_irq(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) xlr_i2c_tx_irq(priv, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!xlr_i2c_busy(priv, status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) wake_up(&priv->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int xlr_i2c_tx(struct xlr_i2c_private *priv, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 *buf, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct i2c_adapter *adap = &priv->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long timeout, stoptime, checktime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int pos, timedout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) offset = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) XLR_I2C_CFG_ADDR | priv->cfg->cfg_extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) stoptime = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) timedout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) xfer = XLR_I2C_STARTXFR_ND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pos = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) xfer = XLR_I2C_STARTXFR_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pos = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) priv->pos = pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* retry can only happen on the first byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (priv->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) while (!timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) checktime = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if ((i2c_status & XLR_I2C_SDOEMPTY) && pos < len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* reset timeout on successful xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) stoptime = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) timedout = time_after(checktime, stoptime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (i2c_status & XLR_I2C_ARB_STARTERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (timedout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (i2c_status & XLR_I2C_ACK_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!xlr_i2c_busy(priv, i2c_status) && pos >= len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(&adap->dev, "I2C transmit timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct i2c_adapter *adap = &priv->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long timeout, stoptime, checktime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int nbytes, timedout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) XLR_I2C_CFG_NOADDR | priv->cfg->cfg_extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) stoptime = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) timedout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) nbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (priv->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) while (!timedout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) checktime = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (i2c_status & XLR_I2C_RXRDY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (nbytes >= len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EIO; /* should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) buf[nbytes++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* reset timeout on successful read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) stoptime = jiffies + timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) timedout = time_after(checktime, stoptime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (i2c_status & XLR_I2C_ARB_STARTERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (timedout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (i2c_status & XLR_I2C_ACK_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!xlr_i2c_busy(priv, i2c_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(&adap->dev, "I2C receive timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int xlr_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct xlr_i2c_private *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (priv->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; ret == 0 && i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) msg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) priv->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (priv->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) priv->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return (ret != 0) ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static u32 xlr_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Emulate SMBUS over I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct i2c_algorithm xlr_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .master_xfer = xlr_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .functionality = xlr_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct i2c_adapter_quirks xlr_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct xlr_i2c_config xlr_i2c_config_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .status_busy = XLR_I2C_BUS_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .cfg_extra = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct xlr_i2c_config xlr_i2c_config_tangox = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = XLR_I2C_FLAG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .status_busy = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .cfg_extra = 1 << 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct of_device_id xlr_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .compatible = "sigma,smp8642-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .data = &xlr_i2c_config_tangox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_DEVICE_TABLE(of, xlr_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int xlr_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct xlr_i2c_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned long clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 busfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) match = of_match_device(xlr_i2c_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->cfg = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) priv->cfg = &xlr_i2c_config_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) priv->iobase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (IS_ERR(priv->iobase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return PTR_ERR(priv->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (irq > 0 && (priv->cfg->flags & XLR_I2C_FLAG_IRQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) priv->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = devm_request_irq(&pdev->dev, priv->irq, xlr_i2c_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) IRQF_SHARED, dev_name(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init_waitqueue_head(&priv->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) &busfreq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) busfreq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clk_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) clk_div = DIV_ROUND_UP(clk_rate, 2 * busfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) xlr_i2c_wreg(priv->iobase, XLR_I2C_CLKDIV, clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) clk_disable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) priv->clk = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) priv->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) priv->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) priv->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) priv->adap.algo_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) priv->adap.algo = &xlr_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) priv->adap.quirks = &xlr_i2c_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) priv->adap.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) priv->adap.class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = i2c_add_numbered_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) goto err_unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_info(&priv->adap.dev, "Added I2C Bus.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) err_unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int xlr_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct xlr_i2c_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) clk_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct platform_driver xlr_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .probe = xlr_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .remove = xlr_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "xlr-i2cbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .of_match_table = xlr_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) module_platform_driver(xlr_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@netlogicmicro.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MODULE_ALIAS("platform:xlr-i2cbus");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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