^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2003-2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c-smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XLP9XX_I2C_DIV 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XLP9XX_I2C_CTRL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define XLP9XX_I2C_CMD 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define XLP9XX_I2C_STATUS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define XLP9XX_I2C_MTXFIFO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define XLP9XX_I2C_MRXFIFO 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define XLP9XX_I2C_MFIFOCTRL 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define XLP9XX_I2C_STXFIFO 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define XLP9XX_I2C_SRXFIFO 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define XLP9XX_I2C_SFIFOCTRL 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define XLP9XX_I2C_SLAVEADDR 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define XLP9XX_I2C_OWNADDR 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define XLP9XX_I2C_FIFOWCNT 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define XLP9XX_I2C_INTEN 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XLP9XX_I2C_INTST 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define XLP9XX_I2C_WAITCNT 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define XLP9XX_I2C_TIMEOUT 0X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define XLP9XX_I2C_GENCALLADDR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define XLP9XX_I2C_STATUS_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define XLP9XX_I2C_CMD_START BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define XLP9XX_I2C_CMD_STOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define XLP9XX_I2C_CMD_READ BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define XLP9XX_I2C_CMD_WRITE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define XLP9XX_I2C_CMD_ACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define XLP9XX_I2C_CTRL_MCTLEN_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define XLP9XX_I2C_CTRL_RST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XLP9XX_I2C_CTRL_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define XLP9XX_I2C_CTRL_MASTER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XLP9XX_I2C_CTRL_FIFORD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define XLP9XX_I2C_CTRL_ADDMODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define XLP9XX_I2C_INTEN_NACKADDR BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define XLP9XX_I2C_INTEN_SADDR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define XLP9XX_I2C_INTEN_DATADONE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define XLP9XX_I2C_INTEN_ARLOST BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define XLP9XX_I2C_INTEN_MFIFOFULL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define XLP9XX_I2C_INTEN_MFIFOEMTY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define XLP9XX_I2C_INTEN_MFIFOHI BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define XLP9XX_I2C_INTEN_BUSERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define XLP9XX_I2C_MFIFOCTRL_RST BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XLP9XX_I2C_SLAVEADDR_RW BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XLP9XX_I2C_IP_CLK_FREQ 133000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XLP9XX_I2C_FIFO_SIZE 0x80U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XLP9XX_I2C_TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define XLP9XX_I2C_BUSY_TIMEOUT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define XLP9XX_I2C_FIFO_WCNT_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define XLP9XX_I2C_STATUS_ERRMASK (XLP9XX_I2C_INTEN_ARLOST | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct xlp9xx_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct i2c_smbus_alert_setup alert_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_client *ara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) bool msg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) bool len_recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bool client_pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 ip_clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 clk_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 *msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel(val, priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return readl(priv->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 inten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 inten;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 thres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (priv->len_recv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* interrupt after the first read to examine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * the length byte before proceeding further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) thres = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) thres = XLP9XX_I2C_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) thres = priv->msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 *buf = priv->msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) priv->msg_buf_remaining -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) priv->msg_buf += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 val, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Update receive length. Re-read len to get the latest value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * and then add 4 to have a minimum value that can be safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * written. This is to account for the byte read above, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * transfer in progress and any delays in the register I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) XLP9XX_I2C_FIFO_WCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) len = max_t(u32, priv->msg_len, len + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (len >= I2C_SMBUS_BLOCK_MAX + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 rlen, *buf = priv->msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) XLP9XX_I2C_FIFO_WCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (priv->len_recv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* read length byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * We expect at least 2 interrupts for I2C_M_RECV_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * transactions. The length is updated during the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * interrupt, and the buffer contents are only copied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * during subsequent interrupts. If in case the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * get merged we would complete the transaction without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * copying out the bytes from RX fifo. To avoid this now we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * drain the fifo as and when data is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * We drained the rlen byte already, decrement total length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * by one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rlen > I2C_SMBUS_BLOCK_MAX || rlen == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rlen = 0; /*abort transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->msg_buf_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) priv->msg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) xlp9xx_i2c_update_rlen(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *buf++ = rlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (priv->client_pec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ++rlen; /* account for error check byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* update remaining bytes and message length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) priv->msg_buf_remaining = rlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) priv->msg_len = rlen + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) xlp9xx_i2c_update_rlen(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) priv->len_recv = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) len = min(priv->msg_buf_remaining, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) for (i = 0; i < len; i++, buf++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) priv->msg_buf_remaining -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->msg_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (priv->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) xlp9xx_i2c_update_rx_fifo_thres(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct xlp9xx_i2c_dev *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (status & XLP9XX_I2C_STATUS_ERRMASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv->msg_err = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* SADDR ACK for SMBUS_QUICK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!priv->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* TX FIFO got empty, fill it up again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (priv->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) xlp9xx_i2c_fill_tx_fifo(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) xlp9xx_i2c_mask_irq(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) XLP9XX_I2C_INTEN_MFIFOEMTY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (status & (XLP9XX_I2C_INTEN_DATADONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) XLP9XX_I2C_INTEN_MFIFOHI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* data is in FIFO, read it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (priv->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) xlp9xx_i2c_drain_rx_fifo(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (status & XLP9XX_I2C_INTEN_DATADONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto xfer_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) xfer_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) complete(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) while (busy_timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) busy_timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!busy_timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * The controller uses 5 * SCL clock internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * So prescale value should be divided by 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prescale = ((prescale - 8) / 5) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) XLP9XX_I2C_CTRL_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int last_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long timeleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 intr_mask, cmd, val, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) priv->msg_buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) priv->msg_buf_remaining = priv->msg_len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) priv->msg_err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) priv->msg_read = (msg->flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) reinit_completion(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Reset FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) XLP9XX_I2C_MFIFOCTRL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* set slave addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Build control word for transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!priv->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) val &= ~XLP9XX_I2C_CTRL_FIFORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) val |= XLP9XX_I2C_CTRL_FIFORD; /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (msg->flags & I2C_M_TEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val &= ~XLP9XX_I2C_CTRL_ADDMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) priv->len_recv = msg->flags & I2C_M_RECV_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) len = priv->len_recv ? I2C_SMBUS_BLOCK_MAX + 2 : msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->client_pec = msg->flags & I2C_CLIENT_PEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* set FIFO threshold if reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (priv->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) xlp9xx_i2c_update_rx_fifo_thres(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* set data length to be transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* fill fifo during tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (!priv->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) xlp9xx_i2c_fill_tx_fifo(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* set interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (priv->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (msg->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) intr_mask |= XLP9XX_I2C_INTEN_SADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (msg->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) intr_mask |= XLP9XX_I2C_INTEN_SADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) xlp9xx_i2c_unmask_irq(priv, intr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* set cmd reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) cmd = XLP9XX_I2C_CMD_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (msg->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) cmd |= (priv->msg_read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (last_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) cmd |= XLP9XX_I2C_CMD_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (timeleft == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(priv->dev, "i2c transfer timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) xlp9xx_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* update msg->len with actual received length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (msg->flags & I2C_M_RECV_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!priv->msg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) msg->len = priv->msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = xlp9xx_i2c_check_bus_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) xlp9xx_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = xlp9xx_i2c_check_bus_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct i2c_algorithm xlp9xx_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .master_xfer = xlp9xx_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .functionality = xlp9xx_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct xlp9xx_i2c_dev *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_dbg(&pdev->dev, "using default input frequency %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) priv->ip_clk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) priv->ip_clk_hz = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else if (freq == 0 || freq > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) priv->clk_hz = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int xlp9xx_i2c_smbus_setup(struct xlp9xx_i2c_dev *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct i2c_client *ara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!priv->alert_data.irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ara = i2c_new_smbus_alert_device(&priv->adapter, &priv->alert_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (IS_ERR(ara))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return PTR_ERR(ara);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) priv->ara = ara;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int xlp9xx_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct xlp9xx_i2c_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (priv->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* SMBAlert irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) priv->alert_data.irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (priv->alert_data.irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) priv->alert_data.irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) xlp9xx_i2c_get_frequency(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) xlp9xx_i2c_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pdev->name, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(&pdev->dev, "IRQ request failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) init_completion(&priv->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) priv->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) priv->adapter.algo = &xlp9xx_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) priv->adapter.class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) priv->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) i2c_set_adapdata(&priv->adapter, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err = i2c_add_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) err = xlp9xx_i2c_smbus_setup(priv, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_dbg(&pdev->dev, "No active SMBus alert %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int xlp9xx_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct xlp9xx_i2c_dev *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) synchronize_irq(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2c_del_adapter(&priv->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct of_device_id xlp9xx_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { .compatible = "netlogic,xlp980-i2c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {"BRCM9007", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {"CAV9007", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static struct platform_driver xlp9xx_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .probe = xlp9xx_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .remove = xlp9xx_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .name = "xlp9xx-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .of_match_table = xlp9xx_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) module_platform_driver(xlp9xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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