^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i2c-xiic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2002-2007 Xilinx Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009-2010 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This code was implemented by Mocean Laboratories AB when porting linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * to the automotive development board Russellville. The copyright holder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * as seen in the header is Intel corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Mocean Laboratories forked off the GNU/Linux platform work into a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * separate company called Pelagicore AB, which committed the code to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Xilinx IIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_data/i2c-xiic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_NAME "xiic-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum xilinx_i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) STATE_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) STATE_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) STATE_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum xiic_endian {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) BIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * struct xiic_i2c - Internal representation of the XIIC I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @dev: Pointer to device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @base: Memory base of the HW registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @wait: Wait queue for callers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @adap: Kernel adapter representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @tx_msg: Messages from above to be sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @lock: Mutual exclusion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @tx_pos: Current pos in TX message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @nmsgs: Number of messages in tx_msg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @rx_msg: Current RX message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @rx_pos: Position within current RX message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @endianness: big/little-endian byte order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @clk: Pointer to AXI4-lite input clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @state: See STATE_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @singlemaster: Indicates bus is single master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct xiic_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) wait_queue_head_t wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct i2c_msg *tx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int tx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int nmsgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct i2c_msg *rx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int rx_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum xiic_endian endianness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) enum xilinx_i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool singlemaster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XIIC_MSB_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Register offsets in bytes from RegisterBase. Three is added to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * base offset to access LSB (IBM style) of the word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Control Register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Status Register masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Interrupt Status Register masks Interrupt occurs when... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* The following constants specify the depth of the FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* The following constants specify groups of interrupts that are typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * enabled or disables at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define XIIC_TX_INTERRUPTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Tx Fifo upper bit masks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * The following constants define the register offsets for the Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * registers. There are some holes in the memory map for reserved addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * to allow other registers to be added and still match the memory map of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * interrupt controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define XIIC_RESET_MASK 0xAUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define XIIC_PM_TIMEOUT 1000 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* timeout waiting for the controller to respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * The following constant is used for the device global interrupt enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * register, to enable all interrupts for the device, this is the only bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int xiic_start_xfer(struct xiic_i2c *i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __xiic_start_xfer(struct xiic_i2c *i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * For the register read and write functions, a little-endian and big-endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * version are necessary. Endianness is detected during the probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Only the least significant byte [doublet] of the register are ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * accessed. This requires an offset of 3 [2] from the base address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * big-endian systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (i2c->endianness == LITTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iowrite8(value, i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) iowrite8(value, i2c->base + reg + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (i2c->endianness == LITTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = ioread8(i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = ioread8(i2c->base + reg + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (i2c->endianness == LITTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) iowrite16(value, i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) iowrite16be(value, i2c->base + reg + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (i2c->endianness == LITTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) iowrite32(value, i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) iowrite32be(value, i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (i2c->endianness == LITTLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = ioread32(i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = ioread32be(i2c->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) xiic_irq_clr(i2c, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) xiic_irq_en(i2c, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u8 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) timeout = jiffies + XIIC_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(i2c->dev, "Failed to clear rx fifo\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int xiic_reinit(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Set receive Fifo depth to maximum (zero based). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Reset Tx Fifo. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* make sure RX fifo is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = xiic_clear_rx_fifo(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void xiic_deinit(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Disable IIC Device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void xiic_read_rx(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u8 bytes_in_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __func__, bytes_in_fifo, xiic_rx_space(i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (bytes_in_fifo > xiic_rx_space(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bytes_in_fifo = xiic_rx_space(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < bytes_in_fifo; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) i2c->rx_msg->buf[i2c->rx_pos++] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* return the actual space left in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 fifo_space = xiic_tx_fifo_space(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int len = xiic_tx_space(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) len = (len > fifo_space) ? fifo_space : len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __func__, len, fifo_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* last message in transfer -> STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data |= XIIC_TX_DYN_STOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void xiic_wakeup(struct xiic_i2c *i2c, int code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) i2c->tx_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) i2c->rx_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) i2c->nmsgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) i2c->state = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) wake_up(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static irqreturn_t xiic_process(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct xiic_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 pend, isr, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Get the interrupt Status from the IPIF. There is no clearing of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * interrupts in the IPIF. Interrupts must be cleared at the source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * To find which interrupts are pending; AND interrupts pending with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * interrupts masked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mutex_lock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pend = isr & ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __func__, ier, isr, pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) i2c->tx_msg, i2c->nmsgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Service requesting interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ((pend & XIIC_INTR_TX_ERROR_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) !(pend & XIIC_INTR_RX_FULL_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* bus arbritration lost, or...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Transmit error _OR_ RX completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * if this happens when RX_FULL is not set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * this is probably a TX error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* dynamic mode seem to suffer from problems if we just flushes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * fifos and the next message is a TX with len 0 (only addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * reset the IP instead of just flush fifos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) xiic_reinit(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (i2c->rx_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) xiic_wakeup(i2c, STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (i2c->tx_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) xiic_wakeup(i2c, STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (pend & XIIC_INTR_RX_FULL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Receive register/FIFO is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) clr |= XIIC_INTR_RX_FULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!i2c->rx_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "%s unexpected RX IRQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) xiic_clear_rx_fifo(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) xiic_read_rx(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (xiic_rx_space(i2c) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* this is the last part of the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i2c->rx_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* also clear TX error if there (RX complete) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "%s end of message, nmsgs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) __func__, i2c->nmsgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* send next message if this wasn't the last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * otherwise the transfer will be finialise when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * receiving the bus not busy interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (i2c->nmsgs > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) i2c->nmsgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i2c->tx_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "%s will start next...\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __xiic_start_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (pend & XIIC_INTR_BNB_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* IIC bus has transitioned to not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) clr |= XIIC_INTR_BNB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* The bus is not busy, disable BusNotBusy interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!i2c->tx_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) xiic_tx_space(i2c) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) xiic_wakeup(i2c, STATE_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) xiic_wakeup(i2c, STATE_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Transmit register/FIFO is empty or ½ empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) clr |= (pend &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!i2c->tx_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "%s unexpected TX IRQ\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) xiic_fill_tx_fifo(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* current message sent and there is space in the fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "%s end of message sent, nmsgs: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __func__, i2c->nmsgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (i2c->nmsgs > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) i2c->nmsgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) i2c->tx_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __xiic_start_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_dbg(i2c->adap.dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "%s Got TX IRQ but no more to do...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* current frame is sent and is last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * make sure to disable tx half
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mutex_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int xiic_bus_busy(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int xiic_busy(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int tries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (i2c->tx_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* In single master mode bus can only be busy, when in use by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * driver. If the register indicates bus being busy for some reason we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * should ignore it, since bus will never be released and i2c will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * stuck forever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (i2c->singlemaster) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* for instance if previous transfer was terminated due to TX error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * it might be that the bus is on it's way to become available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * give it at most 3 ms to wake
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) err = xiic_bus_busy(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) while (err && tries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err = xiic_bus_busy(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void xiic_start_recv(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 rx_watermark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Clear and enable Rx full interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* we want to get all but last byte, because the TX_ERROR IRQ is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * to inidicate error ACK on the address, and negative ack on the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * received byte, so to not mix them receive all but last.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * In the case where there is only one byte to receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * we can check if ERROR and RX full is set at the same time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) rx_watermark = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (rx_watermark > IIC_RX_FIFO_DEPTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rx_watermark = IIC_RX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!(msg->flags & I2C_M_NOSTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* write the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (i2c->nmsgs == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* very last, enable bus not busy as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* the message is tx:ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) i2c->tx_pos = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void xiic_start_send(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct i2c_msg *msg = i2c->tx_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) __func__, msg, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!(msg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* write the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u16 data = i2c_8bit_addr_from_msg(msg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) XIIC_TX_DYN_START_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if ((i2c->nmsgs == 1) && msg->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* no data and last message -> add STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) data |= XIIC_TX_DYN_STOP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) xiic_fill_tx_fifo(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Clear any pending Tx empty, Tx Error and then enable them. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) XIIC_INTR_BNB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static irqreturn_t xiic_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct xiic_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 pend, isr, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Do not processes a devices interrupts if the device has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * interrupts pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pend = isr & ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (pend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void __xiic_start_xfer(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int first = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int fifo_space = xiic_tx_fifo_space(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __func__, i2c->tx_msg, fifo_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!i2c->tx_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) i2c->rx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) i2c->tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) i2c->nmsgs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) i2c->tx_msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) i2c->tx_pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (i2c->tx_msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* we dont date putting several reads in the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) xiic_start_recv(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) xiic_start_send(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (xiic_tx_space(i2c) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* the message could not be completely sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) fifo_space = xiic_tx_fifo_space(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* there are more messages or the current one could not be completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * put into the FIFO, also enable the half empty interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int xiic_start_xfer(struct xiic_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mutex_lock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = xiic_reinit(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __xiic_start_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_unlock(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct xiic_i2c *i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err = pm_runtime_resume_and_get(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) err = xiic_busy(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) i2c->tx_msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) i2c->nmsgs = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err = xiic_start_xfer(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (i2c->state == STATE_DONE), HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) err = (i2c->state == STATE_DONE) ? num : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) i2c->tx_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) i2c->rx_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) i2c->nmsgs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pm_runtime_mark_last_busy(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pm_runtime_put_autosuspend(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static u32 xiic_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct i2c_algorithm xiic_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .master_xfer = xiic_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .functionality = xiic_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct i2c_adapter_quirks xiic_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .max_read_len = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct i2c_adapter xiic_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .class = I2C_CLASS_DEPRECATED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .algo = &xiic_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .quirks = &xiic_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int xiic_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct xiic_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct xiic_i2c_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) i2c->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (IS_ERR(i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return PTR_ERR(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* hook up driver to tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) i2c->adap = xiic_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) i2c_set_adapdata(&i2c->adap, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) i2c->adap.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) i2c->adap.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) snprintf(i2c->adap.name, sizeof(i2c->adap.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DRIVER_NAME " %s", pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mutex_init(&i2c->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) init_waitqueue_head(&i2c->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) i2c->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (IS_ERR(i2c->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (PTR_ERR(i2c->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_err(&pdev->dev, "input clock not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return PTR_ERR(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = clk_prepare_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(&pdev->dev, "Unable to enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pm_runtime_use_autosuspend(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pm_runtime_set_active(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pm_runtime_enable(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) xiic_process, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pdev->name, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_err(&pdev->dev, "Cannot claim IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) i2c->singlemaster =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) of_property_read_bool(pdev->dev.of_node, "single-master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * Detect endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * set, assume that the endianness was wrong and swap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) i2c->endianness = LITTLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Reset is cleared in xiic_reinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) i2c->endianness = BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = xiic_reinit(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(&pdev->dev, "Cannot xiic_reinit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* add i2c adapter to i2c tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = i2c_add_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) xiic_deinit(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* add in known devices to the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) for (i = 0; i < pdata->num_devices; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) i2c_new_client_device(&i2c->adap, pdata->devices + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) err_clk_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int xiic_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct xiic_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* remove adapter & data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) i2c_del_adapter(&i2c->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = pm_runtime_resume_and_get(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) xiic_deinit(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) pm_runtime_put_sync(i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) clk_disable_unprepare(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) pm_runtime_dont_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const struct of_device_id xiic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) { .compatible = "xlnx,xps-iic-2.00.a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MODULE_DEVICE_TABLE(of, xiic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct xiic_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clk_disable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct xiic_i2c *i2c = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = clk_enable(i2c->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_err(dev, "Cannot enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const struct dev_pm_ops xiic_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) xiic_i2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct platform_driver xiic_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .probe = xiic_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .remove = xiic_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .of_match_table = of_match_ptr(xiic_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .pm = &xiic_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) module_platform_driver(xiic_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) MODULE_AUTHOR("info@mocean-labs.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MODULE_DESCRIPTION("Xilinx I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MODULE_ALIAS("platform:"DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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