^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * X-Gene SLIMpro I2C Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014, Applied Micro Circuits Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Feng Kan <fkan@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Hieu Le <hnle@apm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This driver provides support for X-Gene SLIMpro I2C device access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * using the APM X-Gene SLIMpro mailbox driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <acpi/pcc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mailbox_client.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAILBOX_OP_TIMEOUT 1000 /* Operation time out in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAILBOX_I2C_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLIMPRO_IIC_BUS 1 /* Use I2C bus 1 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMBUS_CMD_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BYTE_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WORD_DATA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BLOCK_DATA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLIMPRO_IIC_I2C_PROTOCOL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLIMPRO_IIC_SMB_PROTOCOL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLIMPRO_IIC_READ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLIMPRO_IIC_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IIC_SMB_WITHOUT_DATA_LEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IIC_SMB_WITH_DATA_LEN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLIMPRO_DEBUG_MSG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLIMPRO_MSG_TYPE_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLIMPRO_DBG_SUBTYPE_I2C1READ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLIMPRO_DBGMSG_TYPE_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLIMPRO_DBGMSG_TYPE_MASK 0x0F000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLIMPRO_IIC_DEV_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLIMPRO_IIC_DEV_MASK 0x00800000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLIMPRO_IIC_DEVID_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLIMPRO_IIC_DEVID_MASK 0x007FE000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLIMPRO_IIC_RW_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLIMPRO_IIC_RW_MASK 0x00001000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLIMPRO_IIC_PROTO_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLIMPRO_IIC_PROTO_MASK 0x00000800U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLIMPRO_IIC_ADDRLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLIMPRO_IIC_ADDRLEN_MASK 0x00000700U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLIMPRO_IIC_DATALEN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLIMPRO_IIC_DATALEN_MASK 0x000000FFU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SLIMpro I2C message encode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * dev - Controller number (0-based)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * chip - I2C chip address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * op - SLIMPRO_IIC_READ or SLIMPRO_IIC_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * proto - SLIMPRO_IIC_SMB_PROTOCOL or SLIMPRO_IIC_I2C_PROTOCOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * addrlen - Length of the address field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * datalen - Length of the data field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLIMPRO_IIC_ENCODE_MSG(dev, chip, op, proto, addrlen, datalen) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ((SLIMPRO_DEBUG_MSG << SLIMPRO_MSG_TYPE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ((SLIMPRO_DBG_SUBTYPE_I2C1READ << SLIMPRO_DBGMSG_TYPE_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SLIMPRO_DBGMSG_TYPE_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ((dev << SLIMPRO_IIC_DEV_SHIFT) & SLIMPRO_IIC_DEV_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ((chip << SLIMPRO_IIC_DEVID_SHIFT) & SLIMPRO_IIC_DEVID_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((op << SLIMPRO_IIC_RW_SHIFT) & SLIMPRO_IIC_RW_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ((proto << SLIMPRO_IIC_PROTO_SHIFT) & SLIMPRO_IIC_PROTO_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ((addrlen << SLIMPRO_IIC_ADDRLEN_SHIFT) & SLIMPRO_IIC_ADDRLEN_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ((datalen << SLIMPRO_IIC_DATALEN_SHIFT) & SLIMPRO_IIC_DATALEN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLIMPRO_MSG_TYPE(v) (((v) & 0xF0000000) >> 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Encode for upper address for block data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLIMPRO_IIC_ENCODE_FLAG_BUFADDR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(a) ((u32) (((a) << 30) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) & 0x40000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(a) ((u32) (((a) >> 12) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) & 0x3FF00000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLIMPRO_IIC_ENCODE_ADDR(a) ((a) & 0x000FFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLIMPRO_IIC_MSG_DWORD_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PCC related defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCC_SIGNATURE 0x50424300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCC_STS_CMD_COMPLETE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCC_STS_SCI_DOORBELL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCC_STS_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCC_STS_PLAT_NOTIFY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCC_CMD_GENERATE_DB_INT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct slimpro_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct mbox_chan *mbox_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mbox_client mbox_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int mbox_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct completion rd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* dma_buffer[0] is used for length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 *resp_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) phys_addr_t comm_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void *pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define to_slimpro_i2c_dev(cl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) container_of(cl, struct slimpro_i2c_dev, mbox_client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum slimpro_i2c_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) XGENE_SLIMPRO_I2C_V1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) XGENE_SLIMPRO_I2C_V2 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * This function tests and clears a bitmask then returns its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static u16 xgene_word_tst_and_clr(u16 *addr, u16 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = le16_to_cpu(READ_ONCE(*addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) WRITE_ONCE(*addr, cpu_to_le16(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void slimpro_i2c_rx_cb(struct mbox_client *cl, void *mssg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Response message format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * mssg[0] is the return code of the operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * mssg[1] is the first data word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * mssg[2] is NOT used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ctx->resp_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *ctx->resp_msg = ((u32 *)mssg)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ctx->mbox_client.tx_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) complete(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void slimpro_i2c_pcc_rx_cb(struct mbox_client *cl, void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct slimpro_i2c_dev *ctx = to_slimpro_i2c_dev(cl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Check if platform sends interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!xgene_word_tst_and_clr(&generic_comm_base->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PCC_STS_SCI_DOORBELL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (xgene_word_tst_and_clr(&generic_comm_base->status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PCC_STS_CMD_COMPLETE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) msg = generic_comm_base + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Response message msg[1] contains the return value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ctx->resp_msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *ctx->resp_msg = ((u32 *)msg)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) complete(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void slimpro_i2c_pcc_tx_prepare(struct slimpro_i2c_dev *ctx, u32 *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct acpi_pcct_shared_memory *generic_comm_base = ctx->pcc_comm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 *ptr = (void *)(generic_comm_base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) WRITE_ONCE(generic_comm_base->signature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cpu_to_le32(PCC_SIGNATURE | ctx->mbox_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) WRITE_ONCE(generic_comm_base->command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) cpu_to_le16(SLIMPRO_MSG_TYPE(msg[0]) | PCC_CMD_GENERATE_DB_INT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) status = le16_to_cpu(READ_ONCE(generic_comm_base->status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) status &= ~PCC_STS_CMD_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) WRITE_ONCE(generic_comm_base->status, cpu_to_le16(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Copy the message to the PCC comm space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < SLIMPRO_IIC_MSG_DWORD_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) WRITE_ONCE(ptr[i], cpu_to_le32(msg[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int start_i2c_msg_xfer(struct slimpro_i2c_dev *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ctx->mbox_client.tx_block || !acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!wait_for_completion_timeout(&ctx->rd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) msecs_to_jiffies(MAILBOX_OP_TIMEOUT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Check of invalid data or no device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (*ctx->resp_msg == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int slimpro_i2c_send_msg(struct slimpro_i2c_dev *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ctx->resp_msg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reinit_completion(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) slimpro_i2c_pcc_tx_prepare(ctx, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rc = mbox_send_message(ctx->mbox_chan, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rc = start_i2c_msg_xfer(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mbox_chan_txdone(ctx->mbox_chan, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ctx->resp_msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int slimpro_i2c_rd(struct slimpro_i2c_dev *ctx, u32 chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 addr, u32 addrlen, u32 protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 readlen, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SLIMPRO_IIC_READ, protocol, addrlen, readlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) msg[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return slimpro_i2c_send_msg(ctx, msg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int slimpro_i2c_wr(struct slimpro_i2c_dev *ctx, u32 chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 addr, u32 addrlen, u32 protocol, u32 writelen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SLIMPRO_IIC_WRITE, protocol, addrlen, writelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) msg[1] = SLIMPRO_IIC_ENCODE_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) msg[2] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return slimpro_i2c_send_msg(ctx, msg, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int slimpro_i2c_blkrd(struct slimpro_i2c_dev *ctx, u32 chip, u32 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 addrlen, u32 protocol, u32 readlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 with_data_len, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (dma_mapping_error(ctx->dev, paddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ctx->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) protocol, addrlen, readlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SLIMPRO_IIC_ENCODE_FLAG_WITH_DATA_LEN(with_data_len) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SLIMPRO_IIC_ENCODE_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg[2] = (u32)paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) rc = slimpro_i2c_send_msg(ctx, msg, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Copy to destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) memcpy(data, ctx->dma_buffer, readlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dma_unmap_single(ctx->dev, paddr, readlen, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 addr, u32 addrlen, u32 protocol, u32 writelen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 msg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) memcpy(ctx->dma_buffer, data, writelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (dma_mapping_error(ctx->dev, paddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(&ctx->adapter.dev, "Error in mapping dma buffer %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctx->dma_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) msg[0] = SLIMPRO_IIC_ENCODE_MSG(SLIMPRO_IIC_BUS, chip, SLIMPRO_IIC_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) protocol, addrlen, writelen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) msg[1] = SLIMPRO_IIC_ENCODE_FLAG_BUFADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SLIMPRO_IIC_ENCODE_UPPER_BUFADDR(paddr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SLIMPRO_IIC_ENCODE_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) msg[2] = (u32)paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ctx->mbox_client.tx_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) reinit_completion(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) rc = slimpro_i2c_send_msg(ctx, msg, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dma_unmap_single(ctx->dev, paddr, writelen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int xgene_slimpro_i2c_xfer(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct slimpro_i2c_dev *ctx = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = slimpro_i2c_rd(ctx, addr, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BYTE_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) data->byte = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) BYTE_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data->byte = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = data->byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) BYTE_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = slimpro_i2c_rd(ctx, addr, command, SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) WORD_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) data->word = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val = data->word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = slimpro_i2c_wr(ctx, addr, command, SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) WORD_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = slimpro_i2c_blkrd(ctx, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) I2C_SMBUS_BLOCK_MAX + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) IIC_SMB_WITH_DATA_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) &data->block[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = slimpro_i2c_blkwr(ctx, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SLIMPRO_IIC_SMB_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) data->block[0] + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) &data->block[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (read_write == I2C_SMBUS_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = slimpro_i2c_blkrd(ctx, addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SLIMPRO_IIC_I2C_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) I2C_SMBUS_BLOCK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) IIC_SMB_WITHOUT_DATA_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) &data->block[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = slimpro_i2c_blkwr(ctx, addr, command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SMBUS_CMD_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SLIMPRO_IIC_I2C_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) data->block[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &data->block[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Return list of supported functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static u32 xgene_slimpro_i2c_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) I2C_FUNC_SMBUS_BLOCK_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const struct i2c_algorithm xgene_slimpro_i2c_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .smbus_xfer = xgene_slimpro_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .functionality = xgene_slimpro_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int xgene_slimpro_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct slimpro_i2c_dev *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct i2c_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct mbox_client *cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ctx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) platform_set_drvdata(pdev, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cl = &ctx->mbox_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* Request mailbox channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) init_completion(&ctx->rd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) cl->tx_tout = MAILBOX_OP_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cl->knows_txdone = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cl->tx_block = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cl->rx_callback = slimpro_i2c_rx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ctx->mbox_chan = mbox_request_channel(cl, MAILBOX_I2C_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (IS_ERR(ctx->mbox_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(&pdev->dev, "i2c mailbox channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return PTR_ERR(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct acpi_pcct_hw_reduced *cppc_ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int version = XGENE_SLIMPRO_I2C_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!acpi_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) version = (int)acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (device_property_read_u32(&pdev->dev, "pcc-channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &ctx->mbox_idx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ctx->mbox_idx = MAILBOX_I2C_INDEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cl->tx_block = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cl->rx_callback = slimpro_i2c_pcc_rx_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ctx->mbox_chan = pcc_mbox_request_channel(cl, ctx->mbox_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(ctx->mbox_chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&pdev->dev, "PCC mailbox channel request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return PTR_ERR(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * The PCC mailbox controller driver should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * have parsed the PCCT (global table of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * PCC channels) and stored pointers to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * subspace communication region in con_priv.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cppc_ss = ctx->mbox_chan->con_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (!cppc_ss) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&pdev->dev, "PPC subspace not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rc = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) goto mbox_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!ctx->mbox_chan->mbox->txdone_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(&pdev->dev, "PCC IRQ not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) rc = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) goto mbox_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * This is the shared communication region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * for the OS and Platform to communicate over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctx->comm_base_addr = cppc_ss->base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ctx->comm_base_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (version == XGENE_SLIMPRO_I2C_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ctx->pcc_comm_addr = memremap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ctx->comm_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cppc_ss->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MEMREMAP_WT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ctx->pcc_comm_addr = memremap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ctx->comm_base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cppc_ss->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MEMREMAP_WB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(&pdev->dev, "Failed to get PCC comm region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rc = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) goto mbox_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (!ctx->pcc_comm_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) "Failed to ioremap PCC comm region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) goto mbox_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_warn(&pdev->dev, "Unable to set dma mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Setup I2C adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) adapter = &ctx->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) snprintf(adapter->name, sizeof(adapter->name), "MAILBOX I2C");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) adapter->algo = &xgene_slimpro_i2c_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) adapter->class = I2C_CLASS_HWMON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) adapter->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) adapter->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ACPI_COMPANION_SET(&adapter->dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) i2c_set_adapdata(adapter, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rc = i2c_add_adapter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) goto mbox_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_info(&pdev->dev, "Mailbox I2C Adapter registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mbox_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pcc_mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int xgene_slimpro_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct slimpro_i2c_dev *ctx = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) i2c_del_adapter(&ctx->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (acpi_disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) pcc_mbox_free_channel(ctx->mbox_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct of_device_id xgene_slimpro_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {.compatible = "apm,xgene-slimpro-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_DEVICE_TABLE(of, xgene_slimpro_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct acpi_device_id xgene_slimpro_i2c_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {"APMC0D40", XGENE_SLIMPRO_I2C_V1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {"APMC0D8B", XGENE_SLIMPRO_I2C_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MODULE_DEVICE_TABLE(acpi, xgene_slimpro_i2c_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static struct platform_driver xgene_slimpro_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .probe = xgene_slimpro_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .remove = xgene_slimpro_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "xgene-slimpro-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .of_match_table = of_match_ptr(xgene_slimpro_i2c_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .acpi_match_table = ACPI_PTR(xgene_slimpro_i2c_acpi_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) module_platform_driver(xgene_slimpro_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MODULE_DESCRIPTION("APM X-Gene SLIMpro I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MODULE_AUTHOR("Feng Kan <fkan@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MODULE_AUTHOR("Hieu Le <hnle@apm.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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