^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Wondermedia I2C Master Mode Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from GPLv2+ licensed source:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Copyright (C) 2008 WonderMedia Technologies, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_TCR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_CSR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_ISR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_IMR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_CDR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_TR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_MCR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_SLAVE_CR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_SLAVE_SR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_SLAVE_ISR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_SLAVE_IMR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_SLAVE_DR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_SLAVE_TR 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* REG_CR Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CR_TX_NEXT_ACK 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CR_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CR_TX_NEXT_NO_ACK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CR_TX_END 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CR_CPU_RDY 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLAV_MODE_SEL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* REG_TCR Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TCR_STANDARD_MODE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TCR_MASTER_WRITE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TCR_HS_MODE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TCR_MASTER_READ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TCR_FAST_MODE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TCR_SLAVE_ADDR_MASK 0x007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* REG_ISR Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ISR_NACK_ADDR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ISR_BYTE_END 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ISR_SCL_TIMEOUT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISR_WRITE_ALL 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* REG_IMR Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMR_ENABLE_ALL 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* REG_CSR Bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSR_RCV_NOT_ACK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSR_RCV_ACK_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSR_READY_MASK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* REG_TR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TR_STD 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TR_HS 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* REG_MCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCR_APB_96M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MCR_APB_166M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_MODE_STANDARD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_MODE_FAST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct wmt_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 cmd_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) timeout = jiffies + WMT_I2C_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (i2c_dev->cmd_status & ISR_NACK_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u16 val, tcr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long wait_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int xfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (pmsg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * We still need to run through the while (..) once, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * start at -1 and break out early from the loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) xfer_len = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writew(0, i2c_dev->base + REG_CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val &= ~CR_TX_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val |= CR_CPU_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (i2c_dev->mode == I2C_MODE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tcr_val = TCR_STANDARD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tcr_val = TCR_FAST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writew(tcr_val, i2c_dev->base + REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (pmsg->flags & I2C_M_NOSTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val |= CR_CPU_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) while (xfer_len < pmsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) wait_result = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (wait_result == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = wmt_check_status(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) xfer_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = readw(i2c_dev->base + REG_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (pmsg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (xfer_len == pmsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (last != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writew(CR_ENABLE, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) REG_CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 val, tcr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long wait_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 xfer_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val &= ~CR_TX_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val &= ~CR_TX_NEXT_NO_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!(pmsg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val |= CR_CPU_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (pmsg->len == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val |= CR_TX_NEXT_NO_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (i2c_dev->mode == I2C_MODE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tcr_val = TCR_STANDARD_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tcr_val = TCR_FAST_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) writew(tcr_val, i2c_dev->base + REG_TCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (pmsg->flags & I2C_M_NOSTART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= CR_CPU_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (xfer_len < pmsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) wait_result = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!wait_result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = wmt_check_status(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) xfer_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (xfer_len == pmsg->len - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) val = readw(i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val |= CR_CPU_RDY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writew(val, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int wmt_i2c_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct i2c_msg *pmsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i, is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) for (i = 0; ret >= 0 && i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) is_last = ((i + 1) == num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pmsg = &msgs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (pmsg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = wmt_i2c_read(adap, pmsg, is_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = wmt_i2c_write(adap, pmsg, is_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return (ret < 0) ? ret : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static u32 wmt_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct i2c_algorithm wmt_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .master_xfer = wmt_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .functionality = wmt_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static irqreturn_t wmt_i2c_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct wmt_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* save the status and write-clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) err = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(i2c_dev->dev, "failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err = clk_set_rate(i2c_dev->clk, 20000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) writew(0, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writew(CR_ENABLE, i2c_dev->base + REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) readw(i2c_dev->base + REG_CSR); /* read clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (i2c_dev->mode == I2C_MODE_STANDARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int wmt_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct wmt_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) i2c_dev->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!i2c_dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&pdev->dev, "irq missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) i2c_dev->clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (IS_ERR(i2c_dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_err(&pdev->dev, "unable to request clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return PTR_ERR(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) i2c_dev->mode = I2C_MODE_STANDARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) err = of_property_read_u32(np, "clock-frequency", &clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) i2c_dev->mode = I2C_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "i2c", i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) adap = &i2c_dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) i2c_set_adapdata(adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) adap->algo = &wmt_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) init_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) err = wmt_i2c_reset_hardware(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&pdev->dev, "error initializing hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int wmt_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Disable interrupts, clock and delete adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) writew(0, i2c_dev->base + REG_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) i2c_del_adapter(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct of_device_id wmt_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { .compatible = "wm,wm8505-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct platform_driver wmt_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .probe = wmt_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .remove = wmt_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "wmt-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .of_match_table = wmt_i2c_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) module_platform_driver(wmt_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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