Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)     Philip Edelbrock <phil@netroedge.com>, Kyösti Mälkki <kmalkki@cc.hut.fi>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     Mark D. Studebaker <mdsxyz123@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     Copyright (C) 2005 - 2008  Jean Delvare <jdelvare@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)    Supports the following VIA south bridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)    Chip name          PCI ID  REV     I2C block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)    VT82C596A          0x3050             no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)    VT82C596B          0x3051             no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)    VT82C686A          0x3057  0x30       no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)    VT82C686B          0x3057  0x40       yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)    VT8231             0x8235             no?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)    VT8233             0x3074             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)    VT8233A            0x3147             yes?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)    VT8235             0x3177             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)    VT8237R            0x3227             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)    VT8237A            0x3337             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)    VT8237S            0x3372             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)    VT8251             0x3287             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)    CX700              0x8324             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)    VX800/VX820        0x8353             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)    VX855/VX875        0x8409             yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)    Note: we assume there can only be one device, with one SMBus interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static struct pci_dev *vt596_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SMBBA1		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SMBBA2		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SMBBA3		0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* SMBus address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static unsigned short vt596_smba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SMBHSTSTS	(vt596_smba + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SMBHSTCNT	(vt596_smba + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SMBHSTCMD	(vt596_smba + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SMBHSTADD	(vt596_smba + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SMBHSTDAT0	(vt596_smba + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SMBHSTDAT1	(vt596_smba + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SMBBLKDAT	(vt596_smba + 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* PCI Address Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /* SMBus data in configuration space can be found in two places,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)    We try to select the better one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static unsigned short SMBHSTCFG = 0xD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Other settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MAX_TIMEOUT	500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* VT82C596 constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define VT596_QUICK		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define VT596_BYTE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define VT596_BYTE_DATA		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define VT596_WORD_DATA		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define VT596_PROC_CALL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define VT596_BLOCK_DATA	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define VT596_I2C_BLOCK_DATA	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* If force is set to anything different from 0, we forcibly enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)    VT596. DANGEROUS! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static bool force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) module_param(force, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) MODULE_PARM_DESC(force, "Forcibly enable the SMBus. DANGEROUS!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* If force_addr is set to anything different from 0, we forcibly enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)    the VT596 at the given address. VERY DANGEROUS! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static u16 force_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) module_param_hw(force_addr, ushort, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) MODULE_PARM_DESC(force_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		 "Forcibly enable the SMBus at the given address. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 "EXTREMELY DANGEROUS!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static struct pci_driver vt596_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static struct i2c_adapter vt596_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define FEATURE_I2CBLOCK	(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static unsigned int vt596_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void vt596_dump_regs(const char *msg, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	dev_dbg(&vt596_adapter.dev, "%s: STS=%02x CNT=%02x CMD=%02x ADD=%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		"DAT=%02x,%02x\n", msg, inb_p(SMBHSTSTS), inb_p(SMBHSTCNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		inb_p(SMBHSTDAT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (size == VT596_BLOCK_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 || size == VT596_I2C_BLOCK_DATA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		dev_dbg(&vt596_adapter.dev, "BLK=");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		for (i = 0; i < I2C_SMBUS_BLOCK_MAX / 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			printk("%02x,", inb_p(SMBBLKDAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		dev_dbg(&vt596_adapter.dev, "    ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		for (; i < I2C_SMBUS_BLOCK_MAX - 1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			printk("%02x,", inb_p(SMBBLKDAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		printk("%02x\n", inb_p(SMBBLKDAT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static inline void vt596_dump_regs(const char *msg, u8 size) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Return -1 on error, 0 on success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int vt596_transaction(u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	vt596_dump_regs("Transaction (pre)", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* Make sure the SMBus host is ready to start transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		dev_dbg(&vt596_adapter.dev, "SMBus busy (0x%02x). "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			"Resetting...\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		outb_p(temp, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			dev_err(&vt596_adapter.dev, "SMBus reset failed! "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				"(0x%02x)\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* Start the transaction by setting bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	outb_p(0x40 | size, SMBHSTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	/* We will always wait for a fraction of a second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		temp = inb_p(SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	} while ((temp & 0x01) && (++timeout < MAX_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* If the SMBus is still busy, we give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (timeout == MAX_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		dev_err(&vt596_adapter.dev, "SMBus timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (temp & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		dev_err(&vt596_adapter.dev, "Transaction failed (0x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (temp & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_err(&vt596_adapter.dev, "SMBus collision!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (temp & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		dev_dbg(&vt596_adapter.dev, "No response\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Resetting status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (temp & 0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		outb_p(temp, SMBHSTSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	vt596_dump_regs("Transaction (post)", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Return negative errno on error, 0 on success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static s32 vt596_access(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		unsigned short flags, char read_write, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		size = VT596_QUICK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		size = VT596_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (read_write == I2C_SMBUS_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			outb_p(data->byte, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		size = VT596_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			outb_p(data->word & 0xff, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		size = VT596_WORD_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		outb_p(data->word & 0xff, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		size = VT596_PROC_CALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (!(vt596_features & FEATURE_I2CBLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			goto exit_unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			outb_p(data->block[0], SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		outb_p(command, SMBHSTCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (read_write == I2C_SMBUS_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			u8 len = data->block[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			if (len > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				len = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			outb_p(len, SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			for (i = 1; i <= len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 				outb_p(data->block[i], SMBBLKDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		size = (size == I2C_SMBUS_I2C_BLOCK_DATA) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		       VT596_I2C_BLOCK_DATA : VT596_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		goto exit_unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	outb_p(((addr & 0x7f) << 1) | read_write, SMBHSTADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	status = vt596_transaction(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (size == VT596_PROC_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		read_write = I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if ((read_write == I2C_SMBUS_WRITE) || (size == VT596_QUICK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case VT596_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	case VT596_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		data->byte = inb_p(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case VT596_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case VT596_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	case VT596_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case VT596_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		data->block[0] = inb_p(SMBHSTDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			data->block[0] = I2C_SMBUS_BLOCK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		inb_p(SMBHSTCNT);	/* Reset SMBBLKDAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		for (i = 1; i <= data->block[0]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			data->block[i] = inb_p(SMBBLKDAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) exit_unsupported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	dev_warn(&vt596_adapter.dev, "Unsupported transaction %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static u32 vt596_func(struct i2c_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u32 func = I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	    I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	    I2C_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (vt596_features & FEATURE_I2CBLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		func |= I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct i2c_algorithm smbus_algorithm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.smbus_xfer	= vt596_access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.functionality	= vt596_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct i2c_adapter vt596_adapter = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.owner		= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.algo		= &smbus_algorithm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int vt596_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		       const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unsigned char temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Determine the address of the SMBus areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (force_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		vt596_smba = force_addr & 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		force = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		goto found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if ((pci_read_config_word(pdev, id->driver_data, &vt596_smba)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	    !(vt596_smba & 0x0001)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		/* try 2nd address and config reg. for 596 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (id->device == PCI_DEVICE_ID_VIA_82C596_3 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		    !pci_read_config_word(pdev, SMBBA2, &vt596_smba) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		    (vt596_smba & 0x0001)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			SMBHSTCFG = 0x84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			/* no matches at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			dev_err(&pdev->dev, "Cannot configure "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				"SMBus I/O Base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	vt596_smba &= 0xfff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (vt596_smba == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		dev_err(&pdev->dev, "SMBus base address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			"uninitialized - upgrade BIOS or use "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			"force_addr=0xaddr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	error = acpi_check_region(vt596_smba, 8, vt596_driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!request_region(vt596_smba, 8, vt596_driver.name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		dev_err(&pdev->dev, "SMBus region 0x%x already in use!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			vt596_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	pci_read_config_byte(pdev, SMBHSTCFG, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* If force_addr is set, we program the new address here. Just to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	   sure, we disable the VT596 first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (force_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		pci_write_config_byte(pdev, SMBHSTCFG, temp & 0xfe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		pci_write_config_word(pdev, id->driver_data, vt596_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		pci_write_config_byte(pdev, SMBHSTCFG, temp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		dev_warn(&pdev->dev, "WARNING: SMBus interface set to new "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			 "address 0x%04x!\n", vt596_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	} else if (!(temp & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		if (force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			/* NOTE: This assumes I/O space and other allocations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			 * WERE done by the Bios!  Don't complain if your
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			 * hardware does weird things after enabling this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			 * :') Check for Bios updates before resorting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			 * this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			pci_write_config_byte(pdev, SMBHSTCFG, temp | 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			dev_info(&pdev->dev, "Enabling SMBus device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			dev_err(&pdev->dev, "SMBUS: Error: Host SMBus "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 				"controller not enabled! - upgrade BIOS or "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 				"use force=1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			error = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	dev_dbg(&pdev->dev, "VT596_smba = 0x%X\n", vt596_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	switch (pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	case PCI_DEVICE_ID_VIA_CX700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	case PCI_DEVICE_ID_VIA_VX800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	case PCI_DEVICE_ID_VIA_VX855:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	case PCI_DEVICE_ID_VIA_VX900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	case PCI_DEVICE_ID_VIA_8251:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	case PCI_DEVICE_ID_VIA_8237:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	case PCI_DEVICE_ID_VIA_8237A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	case PCI_DEVICE_ID_VIA_8237S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	case PCI_DEVICE_ID_VIA_8235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	case PCI_DEVICE_ID_VIA_8233A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	case PCI_DEVICE_ID_VIA_8233_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		vt596_features |= FEATURE_I2CBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	case PCI_DEVICE_ID_VIA_82C686_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		/* The VT82C686B (rev 0x40) does support I2C block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		   transactions, but the VT82C686A (rev 0x30) doesn't */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		if (pdev->revision >= 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			vt596_features |= FEATURE_I2CBLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	vt596_adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	snprintf(vt596_adapter.name, sizeof(vt596_adapter.name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		 "SMBus Via Pro adapter at %04x", vt596_smba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	vt596_pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	error = i2c_add_adapter(&vt596_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		pci_dev_put(vt596_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		vt596_pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		goto release_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	/* Always return failure here.  This is to allow other drivers to bind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	 * to this pci device.  We don't really want to have control over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	 * pci device, we only wanted to read as few register values from it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) release_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	release_region(vt596_smba, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct pci_device_id vt596_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	  .driver_data = SMBBA1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596B_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	  .driver_data = SMBBA1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	  .driver_data = SMBBA1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237S),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	  .driver_data = SMBBA1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CX700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX800),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX855),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	{ PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VX900),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	  .driver_data = SMBBA3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	{ 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_DEVICE_TABLE(pci, vt596_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct pci_driver vt596_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	.name		= "vt596_smbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	.id_table	= vt596_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.probe		= vt596_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int __init i2c_vt596_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	return pci_register_driver(&vt596_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void __exit i2c_vt596_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	pci_unregister_driver(&vt596_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	if (vt596_pdev != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		i2c_del_adapter(&vt596_adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		release_region(vt596_smba, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		pci_dev_put(vt596_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		vt596_pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_AUTHOR("Kyosti Malkki <kmalkki@cc.hut.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_DESCRIPTION("vt82c596 SMBus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) module_init(i2c_vt596_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) module_exit(i2c_vt596_exit);