^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define UNIPHIER_I2C_DTRM 0x00 /* TX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UNIPHIER_I2C_DTRM_IRQEN BIT(11) /* enable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UNIPHIER_I2C_DTRM_STA BIT(10) /* start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UNIPHIER_I2C_DTRM_STO BIT(9) /* stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UNIPHIER_I2C_DTRM_NACK BIT(8) /* do not return ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UNIPHIER_I2C_DTRM_RD BIT(0) /* read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHIER_I2C_DREC 0x04 /* RX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHIER_I2C_DREC_MST BIT(14) /* 1 = master, 0 = slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UNIPHIER_I2C_DREC_TX BIT(13) /* 1 = transmit, 0 = receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UNIPHIER_I2C_DREC_STS BIT(12) /* stop condition detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHIER_I2C_DREC_LRB BIT(11) /* no ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNIPHIER_I2C_DREC_LAB BIT(9) /* arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNIPHIER_I2C_DREC_BBN BIT(8) /* bus not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UNIPHIER_I2C_MYAD 0x08 /* slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNIPHIER_I2C_CLK 0x0c /* clock frequency control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UNIPHIER_I2C_BRST 0x10 /* bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UNIPHIER_I2C_BRST_FOEN BIT(1) /* normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UNIPHIER_I2C_BRST_RSCL BIT(0) /* release SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNIPHIER_I2C_HOLD 0x14 /* hold time control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UNIPHIER_I2C_BSTS 0x18 /* bus status monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UNIPHIER_I2C_BSTS_SDA BIT(1) /* readback of SDA line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNIPHIER_I2C_BSTS_SCL BIT(0) /* readback of SCL line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNIPHIER_I2C_NOISE 0x1c /* noise filter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNIPHIER_I2C_SETUP 0x20 /* setup time control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct uniphier_i2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int busy_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static irqreturn_t uniphier_i2c_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct uniphier_i2c_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * This hardware uses edge triggered interrupt. Do not touch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * hardware registers in this handler to make sure to catch the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * interrupt edge. Just send a complete signal and return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) complete(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int uniphier_i2c_xfer_byte(struct i2c_adapter *adap, u32 txdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 *rxdatap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reinit_completion(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) txdata |= UNIPHIER_I2C_DTRM_IRQEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel(txdata, priv->membase + UNIPHIER_I2C_DTRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (unlikely(!time_left)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(&adap->dev, "transaction timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rxdata = readl(priv->membase + UNIPHIER_I2C_DREC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (rxdatap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *rxdatap = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int uniphier_i2c_send_byte(struct i2c_adapter *adap, u32 txdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = uniphier_i2c_xfer_byte(adap, txdata, &rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (unlikely(rxdata & UNIPHIER_I2C_DREC_LAB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (unlikely(rxdata & UNIPHIER_I2C_DREC_LRB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int uniphier_i2c_tx(struct i2c_adapter *adap, u16 addr, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = uniphier_i2c_send_byte(adap, addr << 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) UNIPHIER_I2C_DTRM_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) UNIPHIER_I2C_DTRM_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = uniphier_i2c_send_byte(adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) UNIPHIER_I2C_DTRM_NACK | *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int uniphier_i2c_rx(struct i2c_adapter *adap, u16 addr, u16 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = uniphier_i2c_send_byte(adap, addr << 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) UNIPHIER_I2C_DTRM_STA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) UNIPHIER_I2C_DTRM_NACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) UNIPHIER_I2C_DTRM_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = uniphier_i2c_xfer_byte(adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) len ? 0 : UNIPHIER_I2C_DTRM_NACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &rxdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) *buf++ = rxdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int uniphier_i2c_stop(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return uniphier_i2c_send_byte(adap, UNIPHIER_I2C_DTRM_STO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) UNIPHIER_I2C_DTRM_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int uniphier_i2c_master_xfer_one(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct i2c_msg *msg, bool stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bool is_read = msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool recovery = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = uniphier_i2c_rx(adap, msg->addr, msg->len, msg->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = uniphier_i2c_tx(adap, msg->addr, msg->len, msg->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret == -EAGAIN) /* could not acquire bus. bail out without STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret == -ETIMEDOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* This error is fatal. Needs recovery. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) recovery = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret2 = uniphier_i2c_stop(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Failed to issue STOP. The bus needs recovery. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) recovery = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = ret ?: ret2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (recovery)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int uniphier_i2c_check_bus_busy(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (!(readl(priv->membase + UNIPHIER_I2C_DREC) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) UNIPHIER_I2C_DREC_BBN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (priv->busy_cnt++ > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * If bus busy continues too long, it is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * in a wrong state. Try bus recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) i2c_recover_bus(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->busy_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->busy_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int uniphier_i2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct i2c_msg *msg, *emsg = msgs + num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = uniphier_i2c_check_bus_busy(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for (msg = msgs; msg < emsg; msg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Emit STOP if it is the last message or I2C_M_STOP is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = uniphier_i2c_master_xfer_one(adap, msg, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static u32 uniphier_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct i2c_algorithm uniphier_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .master_xfer = uniphier_i2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .functionality = uniphier_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void uniphier_i2c_reset(struct uniphier_i2c_priv *priv, bool reset_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val = UNIPHIER_I2C_BRST_RSCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val |= reset_on ? 0 : UNIPHIER_I2C_BRST_FOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(val, priv->membase + UNIPHIER_I2C_BRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int uniphier_i2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) UNIPHIER_I2C_BSTS_SCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void uniphier_i2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(val ? UNIPHIER_I2C_BRST_RSCL : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) priv->membase + UNIPHIER_I2C_BRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int uniphier_i2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct uniphier_i2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return !!(readl(priv->membase + UNIPHIER_I2C_BSTS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) UNIPHIER_I2C_BSTS_SDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void uniphier_i2c_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) uniphier_i2c_reset(i2c_get_adapdata(adap), false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct i2c_bus_recovery_info uniphier_i2c_bus_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .get_scl = uniphier_i2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .set_scl = uniphier_i2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .get_sda = uniphier_i2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .unprepare_recovery = uniphier_i2c_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void uniphier_i2c_hw_init(struct uniphier_i2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int cyc = priv->clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) uniphier_i2c_reset(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Bit30-16: clock cycles of tLOW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * "tLow/tHIGH = 5/4" meets both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel((cyc * 5 / 9 << 16) | cyc, priv->membase + UNIPHIER_I2C_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) uniphier_i2c_reset(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int uniphier_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct uniphier_i2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) priv->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (IS_ERR(priv->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return PTR_ERR(priv->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clk_rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(dev, "input clock rate should not be zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) priv->clk_cycle = clk_rate / bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) init_completion(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->adap.algo = &uniphier_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv->adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) priv->adap.dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) strlcpy(priv->adap.name, "UniPhier I2C", sizeof(priv->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->adap.bus_recovery_info = &uniphier_i2c_bus_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) uniphier_i2c_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = devm_request_irq(dev, irq, uniphier_i2c_interrupt, 0, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(dev, "failed to request irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = i2c_add_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int uniphier_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct uniphier_i2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int __maybe_unused uniphier_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int __maybe_unused uniphier_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct uniphier_i2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) uniphier_i2c_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct dev_pm_ops uniphier_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SET_SYSTEM_SLEEP_PM_OPS(uniphier_i2c_suspend, uniphier_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct of_device_id uniphier_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { .compatible = "socionext,uniphier-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_DEVICE_TABLE(of, uniphier_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct platform_driver uniphier_i2c_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .probe = uniphier_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .remove = uniphier_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "uniphier-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .of_match_table = uniphier_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .pm = &uniphier_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) module_platform_driver(uniphier_i2c_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MODULE_DESCRIPTION("UniPhier I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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