^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define UNIPHIER_FI2C_CR 0x00 /* control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define UNIPHIER_FI2C_CR_MST BIT(3) /* master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UNIPHIER_FI2C_CR_STA BIT(2) /* start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UNIPHIER_FI2C_CR_STO BIT(1) /* stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UNIPHIER_FI2C_CR_NACK BIT(0) /* do not return ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UNIPHIER_FI2C_DTTX 0x04 /* TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UNIPHIER_FI2C_DTTX_CMD BIT(8) /* send command (slave addr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UNIPHIER_FI2C_DTTX_RD BIT(0) /* read transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UNIPHIER_FI2C_DTRX 0x04 /* RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UNIPHIER_FI2C_SLAD 0x0c /* slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UNIPHIER_FI2C_CYC 0x10 /* clock cycle control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define UNIPHIER_FI2C_LCTL 0x14 /* clock low period control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define UNIPHIER_FI2C_SSUT 0x18 /* restart/stop setup time control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define UNIPHIER_FI2C_DSUT 0x1c /* data setup time control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define UNIPHIER_FI2C_INT 0x20 /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UNIPHIER_FI2C_IE 0x24 /* interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UNIPHIER_FI2C_IC 0x28 /* interrupt clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define UNIPHIER_FI2C_INT_TE BIT(9) /* TX FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define UNIPHIER_FI2C_INT_RF BIT(8) /* RX FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UNIPHIER_FI2C_INT_TC BIT(7) /* send complete (STOP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNIPHIER_FI2C_INT_RC BIT(6) /* receive complete (STOP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNIPHIER_FI2C_INT_TB BIT(5) /* sent specified bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNIPHIER_FI2C_INT_RB BIT(4) /* received specified bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UNIPHIER_FI2C_INT_NA BIT(2) /* no ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define UNIPHIER_FI2C_INT_AL BIT(1) /* arbitration lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define UNIPHIER_FI2C_SR 0x2c /* status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define UNIPHIER_FI2C_SR_DB BIT(12) /* device busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define UNIPHIER_FI2C_SR_STS BIT(11) /* stop condition detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define UNIPHIER_FI2C_SR_BB BIT(8) /* bus busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define UNIPHIER_FI2C_SR_RFF BIT(3) /* RX FIFO full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define UNIPHIER_FI2C_SR_RNE BIT(2) /* RX FIFO not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define UNIPHIER_FI2C_SR_TNF BIT(1) /* TX FIFO not full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UNIPHIER_FI2C_SR_TFE BIT(0) /* TX FIFO empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UNIPHIER_FI2C_RST 0x34 /* reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UNIPHIER_FI2C_RST_TBRST BIT(2) /* clear TX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UNIPHIER_FI2C_RST_RBRST BIT(1) /* clear RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UNIPHIER_FI2C_RST_RST BIT(0) /* forcible bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UNIPHIER_FI2C_BM 0x38 /* bus monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define UNIPHIER_FI2C_BM_SDAO BIT(3) /* output for SDA line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UNIPHIER_FI2C_BM_SDAS BIT(2) /* readback of SDA line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define UNIPHIER_FI2C_BM_SCLO BIT(1) /* output for SCL line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UNIPHIER_FI2C_BM_SCLS BIT(0) /* readback of SCL line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define UNIPHIER_FI2C_NOISE 0x3c /* noise filter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UNIPHIER_FI2C_TBC 0x40 /* TX byte count setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UNIPHIER_FI2C_RBC 0x44 /* RX byte count setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UNIPHIER_FI2C_TBCM 0x48 /* TX byte count monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UNIPHIER_FI2C_RBCM 0x4c /* RX byte count monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UNIPHIER_FI2C_BRST 0x50 /* bus reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UNIPHIER_FI2C_BRST_FOEN BIT(1) /* normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UNIPHIER_FI2C_BRST_RSCL BIT(0) /* release SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UNIPHIER_FI2C_INT_FAULTS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UNIPHIER_FI2C_INT_STOP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define UNIPHIER_FI2C_RD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define UNIPHIER_FI2C_STOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define UNIPHIER_FI2C_MANUAL_NACK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define UNIPHIER_FI2C_BYTE_WISE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define UNIPHIER_FI2C_DEFER_STOP_COMP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define UNIPHIER_FI2C_FIFO_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct uniphier_fi2c_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct completion comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *membase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 enabled_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int busy_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) spinlock_t lock; /* IRQ synchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bool first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * TX-FIFO stores slave address in it for the first access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Decrement the counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fifo_space--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) while (priv->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (fifo_space-- <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) priv->len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 1 : UNIPHIER_FI2C_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) while (priv->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (fifo_left-- <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) priv->len--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(mask, priv->membase + UNIPHIER_FI2C_IC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) priv->membase + UNIPHIER_FI2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct uniphier_fi2c_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_status &= priv->enabled_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (irq_status & UNIPHIER_FI2C_INT_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) priv->error = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) priv->error = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (priv->flags & UNIPHIER_FI2C_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * work around a hardware bug:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The receive-completed interrupt is never set even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * STOP condition is detected after the address phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * of read transaction fails to get ACK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * To avoid time-out error, we issue STOP here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * but do not wait for its completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * It should be checked after exiting this handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) uniphier_fi2c_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (irq_status & UNIPHIER_FI2C_INT_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!priv->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto data_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) uniphier_fi2c_fill_txfifo(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) uniphier_fi2c_drain_rxfifo(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * If the number of bytes to read is multiple of the FIFO size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * earlier than INT_RB. We wait for INT_RB to confirm the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * completion of the current message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto data_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (priv->len <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel(UNIPHIER_FI2C_CR_MST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) UNIPHIER_FI2C_CR_NACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) priv->membase + UNIPHIER_FI2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) data_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (priv->flags & UNIPHIER_FI2C_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) uniphier_fi2c_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->enabled_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) complete(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) handled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * This controller makes a pause while any bit of the IRQ status is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * asserted. Clear the asserted bit to kick the controller just before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * exiting the handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) uniphier_fi2c_clear_irqs(priv, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool repeat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* do not use TX byte counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(0, priv->membase + UNIPHIER_FI2C_TBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) priv->membase + UNIPHIER_FI2C_DTTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * First chunk of data. For a repeated START condition, do not write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * data to the TX fifo here to avoid the timing issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!repeat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) uniphier_fi2c_fill_txfifo(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) priv->flags |= UNIPHIER_FI2C_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (likely(priv->len < 256)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * If possible, use RX byte counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * It can automatically handle NACK for the last byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) UNIPHIER_FI2C_INT_RB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * The byte counter can not count over 256. In this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * do not use it at all. Drain data when FIFO gets full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * but treat the last portion as a special case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) writel(0, priv->membase + UNIPHIER_FI2C_RBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* set slave address with RD bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) priv->membase + UNIPHIER_FI2C_DTTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) priv->membase + UNIPHIER_FI2C_BRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uniphier_fi2c_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) i2c_recover_bus(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct i2c_msg *msg, bool repeat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) bool stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bool is_read = msg->flags & I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned long time_left, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) priv->len = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) priv->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) priv->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) priv->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) priv->flags |= UNIPHIER_FI2C_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reinit_completion(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) uniphier_fi2c_clear_irqs(priv, U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (is_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) uniphier_fi2c_rx_init(priv, msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) uniphier_fi2c_tx_init(priv, msg->addr, repeat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * For a repeated START condition, writing a slave address to the FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * kicks the controller. So, the UNIPHIER_FI2C_CR register should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * written only for a non-repeated START condition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!repeat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) priv->membase + UNIPHIER_FI2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) priv->enabled_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) uniphier_fi2c_set_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&adap->dev, "transaction timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) uniphier_fi2c_recover(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) (status & UNIPHIER_FI2C_SR_STS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) !(status & UNIPHIER_FI2C_SR_BB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(&adap->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "stop condition was not completed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) uniphier_fi2c_recover(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return priv->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (priv->busy_cnt++ > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * If bus busy continues too long, it is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * in a wrong state. Try bus recovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) uniphier_fi2c_recover(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) priv->busy_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) priv->busy_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct i2c_msg *msg, *emsg = msgs + num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bool repeat = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = uniphier_fi2c_check_bus_busy(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (msg = msgs; msg < emsg; msg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Emit STOP if it is the last message or I2C_M_STOP is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) repeat = !stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct i2c_algorithm uniphier_fi2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .master_xfer = uniphier_fi2c_master_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .functionality = uniphier_fi2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) UNIPHIER_FI2C_BM_SCLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) priv->membase + UNIPHIER_FI2C_BRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) UNIPHIER_FI2C_BM_SDAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .recover_bus = i2c_generic_scl_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .get_scl = uniphier_fi2c_get_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .set_scl = uniphier_fi2c_set_scl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .get_sda = uniphier_fi2c_get_sda,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int cyc = priv->clk_cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tmp |= UNIPHIER_FI2C_CR_MST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) uniphier_fi2c_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Standard-mode: tLOW + tHIGH = 10 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Fast-mode: tLOW + tHIGH = 2.5 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * "tLow/tHIGH = 5/4" meets both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * Standard-mode: tSU;DAT = 250 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Fast-mode: tSU;DAT = 100 ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) uniphier_fi2c_prepare_operation(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int uniphier_fi2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct uniphier_fi2c_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) priv->membase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (IS_ERR(priv->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return PTR_ERR(priv->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(dev, "failed to get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(dev, "input clock rate should not be zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) priv->clk_cycle = clk_rate / bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) init_completion(&priv->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) priv->adap.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) priv->adap.algo = &uniphier_fi2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->adap.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) priv->adap.dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2c_set_adapdata(&priv->adap, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) uniphier_fi2c_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pdev->name, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(dev, "failed to request irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = i2c_add_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int uniphier_fi2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) i2c_del_adapter(&priv->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) uniphier_fi2c_hw_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const struct of_device_id uniphier_fi2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { .compatible = "socionext,uniphier-fi2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct platform_driver uniphier_fi2c_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .probe = uniphier_fi2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .remove = uniphier_fi2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .name = "uniphier-fi2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .of_match_table = uniphier_fi2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pm = &uniphier_fi2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) module_platform_driver(uniphier_fi2c_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags