^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/i2c/busses/i2c-tegra.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BYTES_PER_FIFO_WORD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_CNFG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_CNFG_PACKET_MODE_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_STATUS 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_SL_CNFG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_SL_CNFG_NACK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_SL_CNFG_NEWSL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_SL_ADDR1 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_SL_ADDR2 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_TLOW_SEXT 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_TX_FIFO 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_RX_FIFO 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_PACKET_TRANSFER_STATUS 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_FIFO_CONTROL 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_FIFO_STATUS 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_FIFO_STATUS_TX GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_FIFO_STATUS_RX GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_INT_MASK 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_INT_STATUS 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_INT_BUS_CLR_DONE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_INT_NO_ACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_INT_ARBITRATION_LOST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_CLK_DIVISOR 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DVC_CTRL_REG1 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DVC_CTRL_REG1_INTR_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DVC_CTRL_REG3 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DVC_CTRL_REG3_SW_PROG BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DVC_STATUS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DVC_STATUS_I2C_DONE_INTR BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_ERR_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_ERR_NO_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_ERR_ARBITRATION_LOST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PACKET_HEADER0_PROTOCOL_I2C 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2C_HEADER_CONT_ON_NAK BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2C_HEADER_READ BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2C_HEADER_10BIT_ADDR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2C_HEADER_IE_ENABLE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2C_HEADER_REPEAT_START BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define I2C_HEADER_CONTINUE_XFER BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2C_BUS_CLEAR_CNFG 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2C_BC_STOP_COND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define I2C_BC_TERMINATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define I2C_BC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2C_BUS_CLEAR_STATUS 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I2C_BC_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2C_CONFIG_LOAD 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define I2C_MSTR_CONFIG_LOAD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define I2C_CLKEN_OVERRIDE 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define I2C_MST_CORE_CLKEN_OVR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define I2C_INTERFACE_TIMING_0 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define I2C_INTERFACE_TIMING_1 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define I2C_HS_INTERFACE_TIMING_0 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define I2C_HS_INTERFACE_TIMING_1 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define I2C_MST_FIFO_CONTROL 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I2C_MST_FIFO_STATUS 0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* configuration load timeout in microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define I2C_CONFIG_LOAD_TIMEOUT 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* packet header size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define I2C_PACKET_HEADER_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * avoid DMA overhead, otherwise external APB DMA controller will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * I2C_PACKET_HEADER_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2C_PIO_MODE_PREFERRED_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * msg_end_type: The bus control which needs to be sent at end of transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @MSG_END_STOP: Send stop pulse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @MSG_END_REPEAT_START: Send repeat-start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @MSG_END_CONTINUE: Don't send stop or repeat-start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum msg_end_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MSG_END_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MSG_END_REPEAT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MSG_END_CONTINUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * struct tegra_i2c_hw_feature : per hardware generation features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @has_continue_xfer_support: continue-transfer supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * completion interrupt on per packet basis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @has_config_load_reg: Has the config load register to load the new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @clk_divisor_hs_mode: Clock divisor in HS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @clk_divisor_std_mode: Clock divisor in standard mode. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * applicable if there is no fast clock source i.e. single clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * applicable if there is no fast clock source i.e. single clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * applicable if there is no fast clock source (i.e. single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * clock source).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @has_multi_master_mode: The I2C controller supports running in single-master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * or multi-master mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @has_slcg_override_reg: The I2C controller supports a register that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * overrides the second level clock gating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * provides additional features and allows for longer messages to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * be transferred in one go.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @quirks: I2C adapter quirks for limiting write/read transfer size and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * allowing 0 length transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @supports_bus_clear: Bus Clear support to recover from bus hang during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * SDA stuck low from device for some unknown reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @tlow_std_mode: Low period of the clock in standard mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @thigh_std_mode: High period of the clock in standard mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * in standard mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * conditions in fast/fast-plus modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * in HS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @has_interface_timing_reg: Has interface timing register to program the tuned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * timing settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct tegra_i2c_hw_feature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool has_continue_xfer_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) bool has_per_pkt_xfer_complete_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) bool has_config_load_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 clk_divisor_hs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 clk_divisor_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 clk_divisor_fast_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 clk_divisor_fast_plus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bool has_multi_master_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bool has_slcg_override_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bool has_mst_fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const struct i2c_adapter_quirks *quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bool supports_bus_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bool has_apb_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 tlow_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 thigh_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 tlow_fast_fastplus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 thigh_fast_fastplus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 setup_hold_time_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 setup_hold_time_fast_fast_plus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 setup_hold_time_hs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool has_interface_timing_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * struct tegra_i2c_dev - per device I2C context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @dev: device reference for power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @hw: Tegra I2C HW feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @adapter: core I2C layer adapter information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @div_clk: clock reference for div clock of I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @clocks: array of I2C controller clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @nclocks: number of clocks in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @rst: reset control for the I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @base: ioremapped registers cookie
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @base_phys: physical base address of the I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @cont_id: I2C controller ID, used for packet header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @irq: IRQ number of transfer complete interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @is_dvc: identifies the DVC I2C controller, has a different register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @is_vi: identifies the VI I2C controller, has a different register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @msg_complete: transfer completion notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @msg_err: error code for completed message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @msg_buf: pointer to current message data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @msg_buf_remaining: size of unsent data in the message buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @msg_read: indicates that the transfer is a read access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @bus_clk_rate: current I2C bus clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @multimaster_mode: indicates that I2C controller is in multi-master mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @tx_dma_chan: DMA transmit channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @rx_dma_chan: DMA receive channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @dma_phys: handle to DMA resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @dma_buf: pointer to allocated DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @dma_buf_size: DMA buffer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @dma_mode: indicates active DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @dma_complete: DMA completion notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @atomic_mode: indicates active atomic transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct tegra_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) const struct tegra_i2c_hw_feature *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int cont_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) phys_addr_t base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct clk_bulk_data clocks[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int nclocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct clk *div_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 bus_clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct completion msg_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) size_t msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int msg_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 *msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct completion dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct dma_chan *tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dma_chan *rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int dma_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dma_addr_t dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bool multimaster_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bool atomic_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) bool dma_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bool msg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bool is_dvc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bool is_vi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel_relaxed(val, i2c_dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return readl_relaxed(i2c_dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * If necessary, i2c_writel() and i2c_readl() will offset the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * in order to talk to the I2C block inside the DVC block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (i2c_dev->is_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) else if (i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) reg = 0xc00 + (reg << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* read back register to make sure that register writes completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (reg != I2C_TX_FIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else if (i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int reg, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned int reg, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 *data32 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * VI I2C controller has known hardware bug where writes get stuck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * when immediate multiple writes happen to TX_FIFO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Recommended software work around is to read I2C register after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * each write to TX_FIFO register to flush out the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) while (len--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) i2c_writel(i2c_dev, *data32++, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int reg, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void tegra_i2c_dma_complete(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct tegra_i2c_dev *i2c_dev = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) complete(&i2c_dev->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct dma_async_tx_descriptor *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reinit_completion(&i2c_dev->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) len, dir, DMA_PREP_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!dma_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) i2c_dev->msg_read ? "RX" : "TX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dma_desc->callback = tegra_i2c_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dma_desc->callback_param = i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dmaengine_submit(dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dma_async_issue_pending(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (i2c_dev->dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) i2c_dev->dma_buf, i2c_dev->dma_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) i2c_dev->dma_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (i2c_dev->tx_dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dma_release_channel(i2c_dev->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) i2c_dev->tx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (i2c_dev->rx_dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dma_release_channel(i2c_dev->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) i2c_dev->rx_dma_chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dma_addr_t dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 *dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_dbg(i2c_dev->dev, "DMA support not enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) chan = dma_request_chan(i2c_dev->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) err = PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) i2c_dev->rx_dma_chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chan = dma_request_chan(i2c_dev->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (IS_ERR(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) err = PTR_ERR(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) i2c_dev->tx_dma_chan = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) I2C_PACKET_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) &dma_phys, GFP_KERNEL | __GFP_NOWARN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!dma_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) i2c_dev->dma_buf = dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i2c_dev->dma_phys = dma_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tegra_i2c_release_dma(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (err != -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(i2c_dev->dev, "falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * block. This block is identical to the rest of the I2C blocks, except that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * it only supports master mode, it has registers moved around, and it needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * some extra init to get it into I2C mode. The register moves are handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * by i2c_readl() and i2c_writel().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) val |= DVC_CTRL_REG3_SW_PROG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) val |= DVC_CTRL_REG1_INTR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 reg, u32 mask, u32 delay_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!i2c_dev->atomic_mode && !in_irq())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return readl_relaxed_poll_timeout(addr, val, !(val & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) delay_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) delay_us, timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 mask, val, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (i2c_dev->hw->has_mst_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) I2C_MST_FIFO_CONTROL_RX_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) offset = I2C_MST_FIFO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mask = I2C_FIFO_CONTROL_TX_FLUSH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) I2C_FIFO_CONTROL_RX_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) offset = I2C_FIFO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val = i2c_readl(i2c_dev, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i2c_writel(i2c_dev, val, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(i2c_dev->dev, "failed to flush FIFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!i2c_dev->hw->has_config_load_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 1000, I2C_CONFIG_LOAD_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_err(i2c_dev->dev, "failed to load config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * The reset shouldn't ever fail in practice. The failure will be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * sign of a severe problem that needs to be resolved. Still we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * want to fail the initialization completely because this may break
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * kernel boot up since voltage regulators use I2C. Hence, we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * emit a noisy warning on error, which won't stay unnoticed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * won't hose machine entirely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) err = reset_control_reset(i2c_dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) WARN_ON_ONCE(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (i2c_dev->is_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) tegra_dvc_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (i2c_dev->hw->has_multi_master_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val |= I2C_CNFG_MULTI_MASTER_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) i2c_writel(i2c_dev, val, I2C_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) i2c_writel(i2c_dev, 0, I2C_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tegra_i2c_vi_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) switch (i2c_dev->bus_clk_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) tlow = i2c_dev->hw->tlow_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) thigh = i2c_dev->hw->thigh_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* make sure clock divisor programmed correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2c_dev->hw->clk_divisor_hs_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (i2c_dev->hw->has_interface_timing_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * Configure setup and hold times only when tsu_thd is non-zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Otherwise, preserve the chip default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) err = clk_set_rate(i2c_dev->div_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) i2c_dev->bus_clk_rate * clk_multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) err = tegra_i2c_flush_fifos(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) err = tegra_i2c_wait_for_config_load(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 cnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * NACK interrupt is generated before the I2C controller generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * the STOP condition on the bus. So, wait for 2 clock periods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * before disabling the controller so that the STOP condition has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * been delivered properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cnfg = i2c_readl(i2c_dev, I2C_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (cnfg & I2C_CNFG_PACKET_MODE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return tegra_i2c_wait_for_config_load(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) size_t buf_remaining = i2c_dev->msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int words_to_transfer, rx_fifo_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u8 *buf = i2c_dev->msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * Catch overflow due to message fully sent before the check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * RX FIFO availability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (i2c_dev->hw->has_mst_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* round down to exclude partial word at the end of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (words_to_transfer > rx_fifo_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) words_to_transfer = rx_fifo_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) buf += words_to_transfer * BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) rx_fifo_avail -= words_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * If there is a partial word at the end of buffer, handle it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * manually to prevent overwriting past the end of buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (rx_fifo_avail > 0 && buf_remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * buf_remaining > 3 check not needed as rx_fifo_avail == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * when (words_to_transfer was > rx_fifo_avail) earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * in this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val = i2c_readl(i2c_dev, I2C_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) val = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) memcpy(buf, &val, buf_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) buf_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) rx_fifo_avail--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* RX FIFO must be drained, otherwise it's an Overflow case. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (WARN_ON_ONCE(rx_fifo_avail))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) i2c_dev->msg_buf_remaining = buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) i2c_dev->msg_buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) size_t buf_remaining = i2c_dev->msg_buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned int words_to_transfer, tx_fifo_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u8 *buf = i2c_dev->msg_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (i2c_dev->hw->has_mst_fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* round down to exclude partial word at the end of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * This hunk pushes 4 bytes at a time into the TX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * It's very common to have < 4 bytes, hence there is no word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * to push if we have less than 4 bytes to transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (words_to_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (words_to_transfer > tx_fifo_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) words_to_transfer = tx_fifo_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * Update state before writing to FIFO. Note that this may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * cause us to finish writing all bytes (AKA buf_remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * goes to 0), hence we have a potential for an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * is disabled at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) tx_fifo_avail -= words_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) i2c_dev->msg_buf_remaining = buf_remaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) buf += words_to_transfer * BYTES_PER_FIFO_WORD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * If there is a partial word at the end of buffer, handle it manually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * to prevent reading past the end of buffer, which could cross a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * boundary and fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (tx_fifo_avail > 0 && buf_remaining > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * buf_remaining > 3 check not needed as tx_fifo_avail == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * when (words_to_transfer was > tx_fifo_avail) earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * in this function for non-zero words_to_transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) memcpy(&val, buf, buf_remaining);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) val = le32_to_cpu(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) i2c_dev->msg_buf_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) i2c_dev->msg_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) i2c_writel(i2c_dev, val, I2C_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct tegra_i2c_dev *i2c_dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) status = i2c_readl(i2c_dev, I2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) i2c_readl(i2c_dev, I2C_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) i2c_readl(i2c_dev, I2C_CNFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (status & status_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) tegra_i2c_disable_packet_mode(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (status & I2C_INT_NO_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) i2c_dev->msg_err |= I2C_ERR_NO_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (status & I2C_INT_ARBITRATION_LOST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * I2C transfer is terminated during the bus clear, so skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * processing the other interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Overflow error condition: message fully sent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * with no XFER_COMPLETE interrupt but hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * asks to transfer more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (i2c_dev->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) tegra_i2c_fill_tx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) tegra_i2c_mask_irq(i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) I2C_INT_TX_FIFO_DATA_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) i2c_writel(i2c_dev, status, I2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (i2c_dev->is_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * During message read XFER_COMPLETE interrupt is triggered prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * DMA completion and during message write XFER_COMPLETE interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * triggered after DMA completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * so forcing msg_buf_remaining to 0 in DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (status & I2C_INT_PACKET_XFER_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (i2c_dev->dma_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) i2c_dev->msg_buf_remaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Underflow error condition: XFER_COMPLETE before message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * fully sent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) complete(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* mask all interrupts on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) tegra_i2c_mask_irq(i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) I2C_INT_NO_ACK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) I2C_INT_ARBITRATION_LOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) I2C_INT_PACKET_XFER_COMPLETE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) I2C_INT_TX_FIFO_DATA_REQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) I2C_INT_RX_FIFO_DATA_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (i2c_dev->hw->supports_bus_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) i2c_writel(i2c_dev, status, I2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (i2c_dev->is_dvc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (i2c_dev->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dmaengine_terminate_async(i2c_dev->rx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dmaengine_terminate_async(i2c_dev->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) complete(&i2c_dev->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) complete(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct dma_slave_config slv_config = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 val, reg, dma_burst, reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (i2c_dev->hw->has_mst_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) reg = I2C_MST_FIFO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) reg = I2C_FIFO_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (len & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dma_burst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) else if (len & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dma_burst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dma_burst = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (i2c_dev->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) chan = i2c_dev->rx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) slv_config.src_addr = i2c_dev->base_phys + reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) slv_config.src_maxburst = dma_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (i2c_dev->hw->has_mst_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) chan = i2c_dev->tx_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) slv_config.dst_maxburst = dma_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (i2c_dev->hw->has_mst_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) slv_config.device_fc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) err = dmaengine_slave_config(chan, &slv_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_err(i2c_dev->dev, "falling back to PIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) tegra_i2c_release_dma(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) i2c_dev->dma_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (i2c_dev->hw->has_mst_fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) I2C_MST_FIFO_CONTROL_RX_TRIG(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) val = I2C_FIFO_CONTROL_TX_TRIG(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) I2C_FIFO_CONTROL_RX_TRIG(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) i2c_writel(i2c_dev, val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct completion *complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) unsigned int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ktime_t ktime = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tegra_i2c_isr(i2c_dev->irq, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (completion_done(complete)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) s64 delta = ktime_ms_delta(ktimeout, ktime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return msecs_to_jiffies(delta) ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ktime = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } while (ktime_before(ktime, ktimeout));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct completion *complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned int timeout_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (i2c_dev->atomic_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) enable_irq(i2c_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ret = wait_for_completion_timeout(complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) msecs_to_jiffies(timeout_ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) disable_irq(i2c_dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Under some rare circumstances (like running KASAN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * NFS root) CPU, which handles interrupt, may stuck in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * uninterruptible state for a significant time. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * case we will get timeout if I2C transfer is running on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * a sibling CPU, despite of IRQ being raised.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * In order to handle this rare condition, the IRQ status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * needs to be checked after timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) u32 val, time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) reinit_completion(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) I2C_BC_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) err = tegra_i2c_wait_for_config_load(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) val |= I2C_BC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev_err(i2c_dev->dev, "failed to clear bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (!(val & I2C_BC_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) enum msg_end_type end_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u32 *dma_buf = i2c_dev->dma_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u32 packet_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) FIELD_PREP(PACKET_HEADER0_PROTOCOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PACKET_HEADER0_PROTOCOL_I2C) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (i2c_dev->dma_mode && !i2c_dev->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *dma_buf++ = packet_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) packet_header = msg->len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (i2c_dev->dma_mode && !i2c_dev->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) *dma_buf++ = packet_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) packet_header = I2C_HEADER_IE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (end_state == MSG_END_CONTINUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) packet_header |= I2C_HEADER_CONTINUE_XFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) else if (end_state == MSG_END_REPEAT_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) packet_header |= I2C_HEADER_REPEAT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) packet_header |= msg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) packet_header |= I2C_HEADER_10BIT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (msg->flags & I2C_M_IGNORE_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) packet_header |= I2C_HEADER_CONT_ON_NAK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) packet_header |= I2C_HEADER_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (i2c_dev->dma_mode && !i2c_dev->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) *dma_buf++ = packet_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (i2c_dev->msg_err == I2C_ERR_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* start recovery upon arbitration loss in single master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!i2c_dev->multimaster_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return i2c_recover_bus(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (msg->flags & I2C_M_IGNORE_NAK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EREMOTEIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct i2c_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) enum msg_end_type end_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned long time_left, xfer_time = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) size_t xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) err = tegra_i2c_flush_fifos(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) i2c_dev->msg_buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) i2c_dev->msg_buf_remaining = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) i2c_dev->msg_err = I2C_ERR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) reinit_completion(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (i2c_dev->msg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) xfer_size = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) i2c_dev->dma_buf && !i2c_dev->atomic_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * Transfer time in mSec = Total bits / transfer rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) i2c_dev->bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) tegra_i2c_unmask_irq(i2c_dev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (i2c_dev->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dma_sync_single_for_device(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) i2c_dev->dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) xfer_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dma_sync_single_for_cpu(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) i2c_dev->dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) xfer_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (!i2c_dev->msg_read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) msg->buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dma_sync_single_for_device(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) i2c_dev->dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) xfer_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) tegra_i2c_fill_tx_fifo(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) else if (i2c_dev->msg_buf_remaining)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) tegra_i2c_unmask_irq(i2c_dev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) i2c_readl(i2c_dev, I2C_INT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (i2c_dev->dma_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) time_left = tegra_i2c_wait_completion(i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) &i2c_dev->dma_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) xfer_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * Synchronize DMA first, since dmaengine_terminate_sync()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * performs synchronization after the transfer's termination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * and we want to get a completion if transfer succeeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dmaengine_synchronize(i2c_dev->msg_read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) i2c_dev->rx_dma_chan :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) i2c_dev->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dmaengine_terminate_sync(i2c_dev->msg_read ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) i2c_dev->rx_dma_chan :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) i2c_dev->tx_dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_err(i2c_dev->dev, "DMA transfer timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) dma_sync_single_for_cpu(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) i2c_dev->dma_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) xfer_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) xfer_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) tegra_i2c_mask_irq(i2c_dev, int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (time_left == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_err(i2c_dev->dev, "I2C transfer timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) time_left, completion_done(&i2c_dev->msg_complete),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) i2c_dev->msg_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) i2c_dev->dma_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) err = tegra_i2c_error_recover(i2c_dev, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret = pm_runtime_get_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pm_runtime_put_noidle(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) enum msg_end_type end_type = MSG_END_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (i < (num - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* check whether follow up message is coming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (msgs[i + 1].flags & I2C_M_NOSTART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) end_type = MSG_END_CONTINUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) end_type = MSG_END_REPEAT_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) pm_runtime_put(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return ret ?: i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) i2c_dev->atomic_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = tegra_i2c_xfer(adap, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) i2c_dev->atomic_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static u32 tegra_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (i2c_dev->hw->has_continue_xfer_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ret |= I2C_FUNC_NOSTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const struct i2c_algorithm tegra_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .master_xfer = tegra_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .master_xfer_atomic = tegra_i2c_xfer_atomic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .functionality = tegra_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* payload size is only 12 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const struct i2c_adapter_quirks tegra_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .max_read_len = SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .recover_bus = tegra_i2c_issue_bus_clear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .has_continue_xfer_support = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .has_per_pkt_xfer_complete_irq = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .clk_divisor_hs_mode = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .clk_divisor_std_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .clk_divisor_fast_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .clk_divisor_fast_plus_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .has_config_load_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .has_slcg_override_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .supports_bus_clear = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .has_apb_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .thigh_std_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .setup_hold_time_std_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .setup_hold_time_fast_fast_plus_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .setup_hold_time_hs_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .has_interface_timing_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .has_per_pkt_xfer_complete_irq = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .clk_divisor_hs_mode = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .clk_divisor_std_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .clk_divisor_fast_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .clk_divisor_fast_plus_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .has_config_load_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .has_slcg_override_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .supports_bus_clear = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .has_apb_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .thigh_std_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .setup_hold_time_std_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .setup_hold_time_fast_fast_plus_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .setup_hold_time_hs_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .has_interface_timing_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .has_per_pkt_xfer_complete_irq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .clk_divisor_hs_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .clk_divisor_std_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .clk_divisor_fast_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .clk_divisor_fast_plus_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .has_config_load_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .has_slcg_override_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .supports_bus_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .has_apb_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .thigh_std_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .setup_hold_time_std_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .setup_hold_time_fast_fast_plus_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .setup_hold_time_hs_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .has_interface_timing_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .has_per_pkt_xfer_complete_irq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .clk_divisor_hs_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .clk_divisor_std_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .clk_divisor_fast_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .clk_divisor_fast_plus_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .has_config_load_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .has_slcg_override_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .supports_bus_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .has_apb_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .thigh_std_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .setup_hold_time_std_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .setup_hold_time_fast_fast_plus_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .setup_hold_time_hs_mode = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .has_interface_timing_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .has_per_pkt_xfer_complete_irq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .clk_divisor_hs_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .clk_divisor_std_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .clk_divisor_fast_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .clk_divisor_fast_plus_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .has_config_load_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .has_slcg_override_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .supports_bus_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .has_apb_dma = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .thigh_std_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .setup_hold_time_std_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .setup_hold_time_fast_fast_plus_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .setup_hold_time_hs_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .has_interface_timing_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .has_per_pkt_xfer_complete_irq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .clk_divisor_hs_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .clk_divisor_std_mode = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .clk_divisor_fast_mode = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .clk_divisor_fast_plus_mode = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .has_config_load_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .has_multi_master_mode = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .has_slcg_override_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .has_mst_fifo = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .quirks = &tegra_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .supports_bus_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .has_apb_dma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .tlow_std_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .thigh_std_mode = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .tlow_fast_fastplus_mode = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .setup_hold_time_std_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .setup_hold_time_fast_fast_plus_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .setup_hold_time_hs_mode = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .has_interface_timing_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .has_continue_xfer_support = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .has_per_pkt_xfer_complete_irq = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .clk_divisor_hs_mode = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .clk_divisor_std_mode = 0x4f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .clk_divisor_fast_mode = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .clk_divisor_fast_plus_mode = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .has_config_load_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .has_multi_master_mode = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .has_slcg_override_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .has_mst_fifo = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .quirks = &tegra194_i2c_quirks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .supports_bus_clear = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .has_apb_dma = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .tlow_std_mode = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .thigh_std_mode = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .tlow_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .thigh_fast_fastplus_mode = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .setup_hold_time_std_mode = 0x08080808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .setup_hold_time_fast_fast_plus_mode = 0x02020202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .setup_hold_time_hs_mode = 0x090909,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .has_interface_timing_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static const struct of_device_id tegra_i2c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct device_node *np = i2c_dev->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) bool multi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) err = of_property_read_u32(np, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) &i2c_dev->bus_clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) multi_mode = of_property_read_bool(np, "multi-master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) i2c_dev->multimaster_mode = multi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) i2c_dev->is_dvc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) i2c_dev->is_vi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) i2c_dev->div_clk = i2c_dev->clocks[0].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (!i2c_dev->multimaster_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) err = clk_enable(i2c_dev->div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) goto unprepare_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) unprepare_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (i2c_dev->multimaster_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) clk_disable(i2c_dev->div_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = pm_runtime_get_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret = tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) pm_runtime_put(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int tegra_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct tegra_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) init_completion(&i2c_dev->msg_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) init_completion(&i2c_dev->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) i2c_dev->hw = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) i2c_dev->cont_id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) i2c_dev->base_phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) i2c_dev->irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* interrupt will be enabled during of transfer time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) IRQF_NO_SUSPEND, dev_name(i2c_dev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (IS_ERR(i2c_dev->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) "failed to get reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return PTR_ERR(i2c_dev->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) tegra_i2c_parse_dt(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) err = tegra_i2c_init_clocks(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) err = tegra_i2c_init_dma(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) goto release_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * VI I2C is in VE power domain which is not always ON and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) * non IRQ-safe domain because this prevents powering off the power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) * domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) * be used for atomic transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if (!i2c_dev->is_vi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) pm_runtime_irq_safe(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pm_runtime_enable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) err = tegra_i2c_init_hardware(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) goto release_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) i2c_dev->adapter.dev.parent = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) i2c_dev->adapter.retries = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) i2c_dev->adapter.timeout = 6 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) i2c_dev->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) i2c_dev->adapter.algo = &tegra_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) i2c_dev->adapter.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (i2c_dev->hw->supports_bus_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) sizeof(i2c_dev->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) err = i2c_add_numbered_adapter(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) goto release_rpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) release_rpm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) tegra_i2c_release_dma(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) release_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) tegra_i2c_release_clocks(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static int tegra_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) i2c_del_adapter(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) tegra_i2c_release_dma(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) tegra_i2c_release_clocks(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) err = pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) * VI I2C device is attached to VE power domain which goes through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) * power ON/OFF during runtime PM resume/suspend, meaning that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) * controller needs to be re-initialized after power ON.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (i2c_dev->is_vi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) err = tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) goto disable_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) disable_clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return pinctrl_pm_select_idle_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static int __maybe_unused tegra_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) i2c_mark_adapter_suspended(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (!pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) err = tegra_i2c_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static int __maybe_unused tegra_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) * We need to ensure that clocks are enabled so that registers can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) * restored in tegra_i2c_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) err = tegra_i2c_runtime_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) err = tegra_i2c_init(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) * In case we are runtime suspended, disable clocks again so that we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) * don't unbalance the clock reference counts during the next runtime
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) * resume transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (pm_runtime_status_suspended(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) err = tegra_i2c_runtime_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) i2c_mark_adapter_resumed(&i2c_dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static const struct dev_pm_ops tegra_i2c_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static struct platform_driver tegra_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .probe = tegra_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .remove = tegra_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .name = "tegra-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .of_match_table = tegra_i2c_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .pm = &tegra_i2c_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) module_platform_driver(tegra_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) MODULE_AUTHOR("Colin Cross");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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