^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WAIT_PCLK(n, rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* I2C register address definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SYNQUACER_I2C_REG_BSR (0x00 << 2) // Bus Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SYNQUACER_I2C_REG_BCR (0x01 << 2) // Bus Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SYNQUACER_I2C_REG_CCR (0x02 << 2) // Clock Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SYNQUACER_I2C_REG_ADR (0x03 << 2) // Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SYNQUACER_I2C_REG_DAR (0x04 << 2) // Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SYNQUACER_I2C_REG_FSR (0x06 << 2) // Bus Clock Freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SYNQUACER_I2C_REG_BC2R (0x07 << 2) // Bus Control 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* I2C register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SYNQUACER_I2C_BSR_FBT BIT(0) // First Byte Transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SYNQUACER_I2C_BSR_AAS BIT(2) // Address as Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SYNQUACER_I2C_BSR_TRX BIT(3) // Transfer/Receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SYNQUACER_I2C_BSR_LRB BIT(4) // Last Received Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SYNQUACER_I2C_BSR_AL BIT(5) // Arbitration Lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SYNQUACER_I2C_BSR_RSC BIT(6) // Repeated Start Cond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SYNQUACER_I2C_BSR_BB BIT(7) // Bus Busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SYNQUACER_I2C_BCR_INT BIT(0) // Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SYNQUACER_I2C_BCR_GCAA BIT(2) // Gen. Call Access Ack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYNQUACER_I2C_BCR_ACK BIT(3) // Acknowledge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SYNQUACER_I2C_BCR_MSS BIT(4) // Master Slave Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SYNQUACER_I2C_BCR_SCC BIT(5) // Start Condition Cont.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYNQUACER_I2C_BCR_BEIE BIT(6) // Bus Error Int Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SYNQUACER_I2C_BCR_BER BIT(7) // Bus Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYNQUACER_I2C_CCR_CS_MASK (0x1f) // CCR Clock Period Sel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SYNQUACER_I2C_CCR_EN BIT(5) // Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SYNQUACER_I2C_CSR_CS_MASK (0x3f) // CSR Clock Period Sel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SYNQUACER_I2C_BC2R_SCLL BIT(0) // SCL Low Drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SYNQUACER_I2C_BC2R_SCLS BIT(4) // SCL Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SYNQUACER_I2C_BC2R_SDAS BIT(5) // SDA Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PCLK frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* STANDARD MODE frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SYNQUACER_I2C_CLK_MASTER_STD(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* FAST MODE frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SYNQUACER_I2C_CLK_MASTER_FAST(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* (clkrate <= 18000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* calculate the value of CS bits in CCR register on standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) & SYNQUACER_I2C_CCR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* calculate the value of CS bits in CSR register on standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate) 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* calculate the value of CS bits in CCR register on fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) & SYNQUACER_I2C_CCR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* calculate the value of CS bits in CSR register on fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate) 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* (clkrate > 18000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* calculate the value of CS bits in CCR register on standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) & SYNQUACER_I2C_CCR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* calculate the value of CS bits in CSR register on standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) & SYNQUACER_I2C_CSR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* calculate the value of CS bits in CCR register on fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) & SYNQUACER_I2C_CCR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* calculate the value of CS bits in CSR register on fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) & SYNQUACER_I2C_CSR_CS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* min I2C clock frequency 14M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SYNQUACER_I2C_MIN_CLK_RATE (14 * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* max I2C clock frequency 200M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SYNQUACER_I2C_MAX_CLK_RATE (200 * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* I2C clock frequency 18M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SYNQUACER_I2C_CLK_RATE_18M (18 * 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SYNQUACER_I2C_SPEED_FM 400 // Fast Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SYNQUACER_I2C_SPEED_SM 100 // Standard Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum i2c_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) STATE_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) STATE_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) STATE_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) STATE_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct synquacer_i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 msg_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 pclkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 speed_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 timeout_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) enum i2c_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline int is_lastmsg(struct synquacer_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return i2c->msg_idx >= (i2c->msg_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline int is_msglast(struct synquacer_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return i2c->msg_ptr == (i2c->msg->len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline int is_msgend(struct synquacer_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return i2c->msg_ptr >= i2c->msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long bit_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (i = 0; i < num; i++, msgs++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bit_count += msgs->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * clear IRQ (INT=0, BER=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * set Stop Condition (MSS=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Interrupt Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) i2c->msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) i2c->msg_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) i2c->msg_idx = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) complete(&i2c->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned char ccr_cs, csr_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 rt = i2c->pclkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Set own Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Set PCLK frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i2c->base + SYNQUACER_I2C_REG_FSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) switch (i2c->speed_khz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case SYNQUACER_I2C_SPEED_FM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Set Clock and enable, Set fast mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SYNQUACER_I2C_CCR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) i2c->base + SYNQUACER_I2C_REG_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case SYNQUACER_I2C_SPEED_SM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Set Clock and enable, Set standard mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) i2c->base + SYNQUACER_I2C_REG_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* clear IRQ (INT=0, BER=0), Interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Disable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) WAIT_PCLK(100, i2c->pclkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct i2c_msg *pmsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned char bsr, bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Generate Start Condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if ((bsr & SYNQUACER_I2C_BSR_BB) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) !(bcr & SYNQUACER_I2C_BCR_MSS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(i2c->dev, "bus is busy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_dbg(i2c->dev, "Continuous Start");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) writeb(bcr | SYNQUACER_I2C_BCR_SCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (bcr & SYNQUACER_I2C_BCR_MSS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_dbg(i2c->dev, "not in master mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_dbg(i2c->dev, "Start Condition");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Start Condition + Enable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writeb(bcr | SYNQUACER_I2C_BCR_MSS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) WAIT_PCLK(10, i2c->pclkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* get BSR & BCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if ((bsr & SYNQUACER_I2C_BSR_AL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) !(bcr & SYNQUACER_I2C_BCR_MSS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dev_dbg(i2c->dev, "arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned char bsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) synquacer_i2c_hw_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (bsr & SYNQUACER_I2C_BSR_BB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(i2c->dev, "cannot get bus (bus busy)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) reinit_completion(&i2c->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) i2c->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i2c->msg_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) i2c->msg_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = synquacer_i2c_master_start(i2c, i2c->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_dbg(i2c->dev, "Address failed: (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) timeout = wait_for_completion_timeout(&i2c->completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msecs_to_jiffies(i2c->timeout_ms));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_dbg(i2c->dev, "timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = i2c->msg_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret != num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* wait 2 clock periods to ensure the stop has been through the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct synquacer_i2c *i2c = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned char bsr, bcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (bcr & SYNQUACER_I2C_BCR_BER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(i2c->dev, "bus error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if ((bsr & SYNQUACER_I2C_BSR_AL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) !(bcr & SYNQUACER_I2C_BCR_MSS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_dbg(i2c->dev, "arbitration lost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) switch (i2c->state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case STATE_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (bsr & SYNQUACER_I2C_BSR_LRB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_dbg(i2c->dev, "ack was not received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (i2c->msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) i2c->state = STATE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) i2c->state = STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (is_lastmsg(i2c) && i2c->msg->len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) synquacer_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (i2c->state == STATE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) goto prepare_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case STATE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (bsr & SYNQUACER_I2C_BSR_LRB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_dbg(i2c->dev, "WRITE: No Ack\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!is_msgend(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writeb(i2c->msg->buf[i2c->msg_ptr++],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i2c->base + SYNQUACER_I2C_REG_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* clear IRQ, and continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writeb(SYNQUACER_I2C_BCR_BEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) SYNQUACER_I2C_BCR_MSS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SYNQUACER_I2C_BCR_INTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (is_lastmsg(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) synquacer_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_dbg(i2c->dev, "WRITE: Next Message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) i2c->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* send the new start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = synquacer_i2c_master_start(i2c, i2c->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_dbg(i2c->dev, "restart error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case STATE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) i2c->msg->buf[i2c->msg_ptr++] = byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else /* address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) prepare_read:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (is_msglast(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writeb(SYNQUACER_I2C_BCR_MSS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SYNQUACER_I2C_BCR_BEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) SYNQUACER_I2C_BCR_INTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!is_msgend(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) writeb(SYNQUACER_I2C_BCR_MSS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SYNQUACER_I2C_BCR_BEIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SYNQUACER_I2C_BCR_INTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SYNQUACER_I2C_BCR_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) i2c->base + SYNQUACER_I2C_REG_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (is_lastmsg(i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* last message, send stop and complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_dbg(i2c->dev, "READ: Send Stop\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) synquacer_i2c_stop(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_dbg(i2c->dev, "READ: Next Transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) i2c->msg_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) i2c->msg_idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) i2c->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = synquacer_i2c_master_start(i2c, i2c->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_dbg(i2c->dev, "restart error (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) synquacer_i2c_stop(i2c, -EAGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i2c->state = STATE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) WAIT_PCLK(10, i2c->pclkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct synquacer_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) i2c = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (retry = 0; retry <= adap->retries; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = synquacer_i2c_doxfer(i2c, msgs, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) synquacer_i2c_hw_reset(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static u32 synquacer_i2c_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct i2c_algorithm synquacer_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .master_xfer = synquacer_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .functionality = synquacer_i2c_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct i2c_adapter synquacer_i2c_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .name = "synquacer_i2c-adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .algo = &synquacer_i2c_algo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .retries = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int synquacer_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct synquacer_i2c *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 bus_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) bus_speed = i2c_acpi_find_bus_speed(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!bus_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) device_property_read_u32(&pdev->dev, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &bus_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &i2c->pclkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (PTR_ERR(i2c->pclk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!IS_ERR_OR_NULL(i2c->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = clk_prepare_enable(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_err(&pdev->dev, "failed to enable clock (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) i2c->pclkrate = clk_get_rate(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(&pdev->dev, "PCLK missing or out of range (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) i2c->pclkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) i2c->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (IS_ERR(i2c->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return PTR_ERR(i2c->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) i2c->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (i2c->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0, dev_name(&pdev->dev), i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) i2c->state = STATE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) i2c->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) i2c->adapter = synquacer_i2c_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) i2c_set_adapdata(&i2c->adapter, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) i2c->adapter.dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) i2c->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ACPI_COMPANION_SET(&i2c->adapter.dev, ACPI_COMPANION(&pdev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) i2c->adapter.nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) init_completion(&i2c->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (bus_speed < I2C_MAX_FAST_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) i2c->speed_khz = SYNQUACER_I2C_SPEED_SM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) i2c->speed_khz = SYNQUACER_I2C_SPEED_FM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) synquacer_i2c_hw_init(i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = i2c_add_numbered_adapter(&i2c->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(&pdev->dev, "failed to add bus to i2c core\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) platform_set_drvdata(pdev, i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_name(&i2c->adapter.dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int synquacer_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct synquacer_i2c *i2c = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) i2c_del_adapter(&i2c->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!IS_ERR(i2c->pclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) clk_disable_unprepare(i2c->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct of_device_id synquacer_i2c_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { .compatible = "socionext,synquacer-i2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct acpi_device_id synquacer_i2c_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { "SCX0003" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static struct platform_driver synquacer_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .probe = synquacer_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .remove = synquacer_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .name = "synquacer_i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .of_match_table = of_match_ptr(synquacer_i2c_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) module_platform_driver(synquacer_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_AUTHOR("Fujitsu Semiconductor Ltd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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