^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * P2WI (Push-Pull Two Wire Interface) bus driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * version 2. This program is licensed "as is" without any warranty of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The P2WI controller looks like an SMBus controller which only supports byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * data transfers. But, it differs from standard SMBus protocol on several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * aspects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - it supports only one slave device, and thus drop the address field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * - it adds a parity bit every 8bits of data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * - only one read access is required to read a byte (instead of a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * followed by a read access in standard SMBus protocol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * - there's no Ack bit after each byte transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * This means this bus cannot be used to interface with standard SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * devices (the only known device to support this interface is the AXP221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * PMIC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* P2WI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define P2WI_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define P2WI_CCR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define P2WI_INTE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define P2WI_INTS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define P2WI_DADDR0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define P2WI_DADDR1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define P2WI_DLEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define P2WI_DATA0 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define P2WI_DATA1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define P2WI_LCR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define P2WI_PMCR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define P2WI_CTRL_START_TRANS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define P2WI_CTRL_ABORT_TRANS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define P2WI_CTRL_GLOBAL_INT_ENB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define P2WI_CTRL_SOFT_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* CLK CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define P2WI_CCR_SDA_OUT_DELAY(v) (((v) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define P2WI_CCR_MAX_CLK_DIV 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define P2WI_CCR_CLK_DIV(v) ((v) & P2WI_CCR_MAX_CLK_DIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* STATUS fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define P2WI_INTS_TRANS_ERR_ID(v) (((v) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define P2WI_INTS_LOAD_BSY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define P2WI_INTS_TRANS_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define P2WI_INTS_TRANS_OVER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* DATA LENGTH fields*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define P2WI_DLEN_READ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define P2WI_DLEN_DATA_LENGTH(v) ((v - 1) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* LINE CTRL fields*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define P2WI_LCR_SCL_STATE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define P2WI_LCR_SDA_STATE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define P2WI_LCR_SCL_CTL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define P2WI_LCR_SCL_CTL_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define P2WI_LCR_SDA_CTL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define P2WI_LCR_SDA_CTL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PMU MODE CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define P2WI_PMCR_PMU_INIT_SEND BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define P2WI_PMCR_PMU_INIT_DATA(v) (((v) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define P2WI_PMCR_PMU_MODE_REG(v) (((v) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define P2WI_PMCR_PMU_DEV_ADDR(v) ((v) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define P2WI_MAX_FREQ 6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct p2wi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static irqreturn_t p2wi_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct p2wi *p2wi = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) status = readl(p2wi->regs + P2WI_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) p2wi->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) status &= (P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) P2WI_INTS_TRANS_OVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(status, p2wi->regs + P2WI_INTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) complete(&p2wi->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static u32 p2wi_functionality(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return I2C_FUNC_SMBUS_BYTE_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int p2wi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 command, int size, union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct p2wi *p2wi = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long dlen = P2WI_DLEN_DATA_LENGTH(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (p2wi->slave_addr >= 0 && addr != p2wi->slave_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(&adap->dev, "invalid P2WI address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(command, p2wi->regs + P2WI_DADDR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dlen |= P2WI_DLEN_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel(data->byte, p2wi->regs + P2WI_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writel(dlen, p2wi->regs + P2WI_DLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (readl(p2wi->regs + P2WI_CTRL) & P2WI_CTRL_START_TRANS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_err(&adap->dev, "P2WI bus busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reinit_completion(&p2wi->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) p2wi->regs + P2WI_INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) p2wi->regs + P2WI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) wait_for_completion(&p2wi->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (p2wi->status & P2WI_INTS_LOAD_BSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(&adap->dev, "P2WI bus busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (p2wi->status & P2WI_INTS_TRANS_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(&adap->dev, "P2WI bus xfer error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (read_write == I2C_SMBUS_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) data->byte = readl(p2wi->regs + P2WI_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct i2c_algorithm p2wi_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .smbus_xfer = p2wi_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .functionality = p2wi_functionality,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id p2wi_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "allwinner,sun6i-a31-p2wi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_DEVICE_TABLE(of, p2wi_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int p2wi_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct device_node *childnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long parent_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct p2wi *p2wi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) of_property_read_u32(np, "clock-frequency", &clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (clk_freq > P2WI_MAX_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "required clock-frequency (%u Hz) is too high (max = 6MHz)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (of_get_child_count(np) > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(dev, "P2WI only supports one slave device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) p2wi = devm_kzalloc(dev, sizeof(struct p2wi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!p2wi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) p2wi->slave_addr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Authorize a p2wi node without any children to be able to use an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * i2c-dev from userpace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * In this case the slave_addr is set to -1 and won't be checked when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * launching a P2WI transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) childnp = of_get_next_available_child(np, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (childnp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = of_property_read_u32(childnp, "reg", &slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(dev, "invalid slave address on node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) childnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) p2wi->slave_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) p2wi->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (IS_ERR(p2wi->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PTR_ERR(p2wi->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) strlcpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) p2wi->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(p2wi->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = PTR_ERR(p2wi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dev, "failed to retrieve clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = clk_prepare_enable(p2wi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(dev, "failed to enable clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) parent_clk_freq = clk_get_rate(p2wi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (IS_ERR(p2wi->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = PTR_ERR(p2wi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = reset_control_deassert(p2wi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_err(dev, "failed to deassert reset line: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto err_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) init_completion(&p2wi->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) p2wi->adapter.dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) p2wi->adapter.algo = &p2wi_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) p2wi->adapter.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) p2wi->adapter.dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) platform_set_drvdata(pdev, p2wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) i2c_set_adapdata(&p2wi->adapter, p2wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = devm_request_irq(dev, irq, p2wi_interrupt, 0, pdev->name, p2wi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev_err(dev, "can't register interrupt handler irq%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) goto err_reset_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_div = parent_clk_freq / clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "clock-frequency is too high, setting it to %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) parent_clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "clock-frequency is too low, setting it to %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) parent_clk_freq / P2WI_CCR_MAX_CLK_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) clk_div = P2WI_CCR_MAX_CLK_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) p2wi->regs + P2WI_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = i2c_add_adapter(&p2wi->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err_reset_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) reset_control_assert(p2wi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) err_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clk_disable_unprepare(p2wi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int p2wi_remove(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct p2wi *p2wi = platform_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) reset_control_assert(p2wi->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk_disable_unprepare(p2wi->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i2c_del_adapter(&p2wi->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct platform_driver p2wi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .probe = p2wi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .remove = p2wi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "i2c-sunxi-p2wi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .of_match_table = p2wi_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) module_platform_driver(p2wi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DESCRIPTION("Allwinner P2WI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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