^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2012 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Linus Walleij <linus.walleij@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* the name of this kernel module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NAME "stu300"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* CR (Control Register) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define I2C_CR (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define I2C_CR_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define I2C_CR_RESET_UMASK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define I2C_CR_DDC1_ENABLE (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C_CR_TRANS_ENABLE (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C_CR_PERIPHERAL_ENABLE (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C_CR_DDC2B_ENABLE (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C_CR_START_ENABLE (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define I2C_CR_ACK_ENABLE (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define I2C_CR_STOP_ENABLE (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define I2C_CR_INTERRUPT_ENABLE (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* SR1 (Status Register 1) 8bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define I2C_SR1 (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define I2C_SR1_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define I2C_SR1_RESET_UMASK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define I2C_SR1_EVF_IND (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define I2C_SR1_ADD10_IND (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define I2C_SR1_TRA_IND (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define I2C_SR1_BUSY_IND (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define I2C_SR1_BTF_IND (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define I2C_SR1_ADSL_IND (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define I2C_SR1_MSL_IND (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define I2C_SR1_SB_IND (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SR2 (Status Register 2) 8bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define I2C_SR2 (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define I2C_SR2_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define I2C_SR2_RESET_UMASK (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_SR2_MASK (0xBF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C_SR2_SCLFAL_IND (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C_SR2_ENDAD_IND (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C_SR2_AF_IND (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2C_SR2_STOPF_IND (0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C_SR2_ARLO_IND (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C_SR2_BERR_IND (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C_SR2_DDC2BF_IND (0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* CCR (Clock Control Register) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_CCR (0x0000000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_CCR_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_CCR_RESET_UMASK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_CCR_MASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_CCR_FMSM (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_CCR_CC_MASK (0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* OAR1 (Own Address Register 1) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2C_OAR1 (0x00000010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_OAR1_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_OAR1_RESET_UMASK (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define I2C_OAR1_ADD_MASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* OAR2 (Own Address Register 2) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2C_OAR2 (0x00000014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2C_OAR2_RESET_VALUE (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define I2C_OAR2_RESET_UMASK (0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define I2C_OAR2_MASK (0xE6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define I2C_OAR2_FR_25_10MHZ (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define I2C_OAR2_FR_10_1667MHZ (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define I2C_OAR2_FR_1667_2667MHZ (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define I2C_OAR2_FR_2667_40MHZ (0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define I2C_OAR2_FR_40_5333MHZ (0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C_OAR2_FR_5333_66MHZ (0xA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C_OAR2_FR_66_80MHZ (0xC0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2C_OAR2_FR_80_100MHZ (0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define I2C_OAR2_FR_MASK (0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define I2C_OAR2_ADD_MASK (0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* DR (Data Register) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define I2C_DR (0x00000018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define I2C_DR_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define I2C_DR_RESET_UMASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define I2C_DR_D_MASK (0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* ECCR (Extended Clock Control Register) 8bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define I2C_ECCR (0x0000001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define I2C_ECCR_RESET_VALUE (0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define I2C_ECCR_RESET_UMASK (0xE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define I2C_ECCR_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define I2C_ECCR_CC_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * These events are more or less responses to commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * sent into the hardware, presumably reflecting the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * of an internal state machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum stu300_event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) STU300_EVENT_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) STU300_EVENT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) STU300_EVENT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) STU300_EVENT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) STU300_EVENT_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) STU300_EVENT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) STU300_EVENT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) STU300_EVENT_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) STU300_EVENT_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) STU300_EVENT_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum stu300_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) STU300_ERROR_NONE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) STU300_ERROR_ACKNOWLEDGE_FAILURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) STU300_ERROR_BUS_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) STU300_ERROR_ARBITRATION_LOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) STU300_ERROR_UNKNOWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* timeout waiting for the controller to respond */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define STU300_TIMEOUT (msecs_to_jiffies(1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The number of address send athemps tried before giving up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * If the first one fails it seems like 5 to 8 attempts are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define NUM_ADDR_RESEND_ATTEMPTS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* I2C clock speed, in Hz 0-400kHz*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static unsigned int scl_frequency = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) module_param(scl_frequency, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * struct stu300_dev - the stu300 driver state holder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @pdev: parent platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @adapter: corresponding I2C adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @clk: hardware block clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @irq: assigned interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @cmd_issue_lock: this locks the following cmd_ variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @cmd_complete: acknowledge completion for an I2C command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @cmd_event: expected event coming in as a response to a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @cmd_err: error code as response to a command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @speed: current bus speed in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @msg_index: index of current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @msg_len: length of current message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct stu300_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct i2c_adapter adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spinlock_t cmd_issue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct completion cmd_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum stu300_event cmd_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum stu300_error cmd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int msg_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int msg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Local forward function declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int stu300_init_hw(struct stu300_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * The block needs writes in both MSW and LSW in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * for all data lines to reach their destination.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline void stu300_wr8(u32 value, void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel((value << 16) | value, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * This merely masks off the duplicates which appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * in bytes 1-3. You _MUST_ use 32-bit bus access on this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * device, else it will not work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline u32 stu300_r8(void __iomem *address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return readl(address) & 0x000000FFU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void stu300_irq_enable(struct stu300_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = stu300_r8(dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val |= I2C_CR_INTERRUPT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Twice paranoia (possible HW glitch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void stu300_irq_disable(struct stu300_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) val = stu300_r8(dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) val &= ~I2C_CR_INTERRUPT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Twice paranoia (possible HW glitch) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Tells whether a certain event or events occurred in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * response to a command. The events represent states in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * the internal state machine of the hardware. The events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * are not very well described in the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * documentation and can only be treated as abstract state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * machine states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @ret 0 = event has not occurred or unknown error, any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * other value means the correct event occurred or an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int stu300_event_occurred(struct stu300_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum stu300_event mr_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* What event happened? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) status1 = stu300_r8(dev->virtbase + I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!(status1 & I2C_SR1_EVF_IND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* No event at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) status2 = stu300_r8(dev->virtbase + I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Block any multiple interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) stu300_irq_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Check for errors first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (status2 & I2C_SR2_AF_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else if (status2 & I2C_SR2_BERR_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev->cmd_err = STU300_ERROR_BUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else if (status2 & I2C_SR2_ARLO_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) switch (mr_event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case STU300_EVENT_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (status1 & I2C_SR1_ADSL_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case STU300_EVENT_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case STU300_EVENT_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) case STU300_EVENT_7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case STU300_EVENT_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (status1 & I2C_SR1_BTF_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case STU300_EVENT_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (status2 & I2C_SR2_STOPF_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case STU300_EVENT_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (status1 & I2C_SR1_SB_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Clear start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case STU300_EVENT_6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (status2 & I2C_SR2_ENDAD_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* First check for any errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case STU300_EVENT_9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (status1 & I2C_SR1_ADD10_IND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* If we get here, we're on thin ice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Here we are in a status where we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * gotten a response that does not match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * what we requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev->cmd_err = STU300_ERROR_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mr_event, status1, status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static irqreturn_t stu300_irh(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct stu300_dev *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Just make sure that the block is clocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) clk_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* See if this was what we were waiting for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) res = stu300_event_occurred(dev, dev->cmd_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (res || dev->cmd_err != STU300_ERROR_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) complete(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) clk_disable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Sends a command and then waits for the bits masked by *flagmask*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * to go high or low by IRQ awaiting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int stu300_start_and_await_event(struct stu300_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 cr_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) enum stu300_event mr_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Lock command issue, fill in an event we wait for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irq(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev->cmd_err = STU300_ERROR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev->cmd_event = mr_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spin_unlock_irq(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Turn on interrupt, send command and wait. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cr_value |= I2C_CR_INTERRUPT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) stu300_wr8(cr_value, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) STU300_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "wait_for_completion_interruptible_timeout() "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "returned %d waiting for event %04x\n", ret, mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(&dev->pdev->dev, "controller timed out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "waiting for event %d, reinit hardware\n", mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (void) stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (dev->cmd_err != STU300_ERROR_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(&dev->pdev->dev, "controller (start) "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "error %d waiting for event %d, reinit hardware\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev->cmd_err, mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) (void) stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * This waits for a flag to be set, if it is not set on entry, an interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * configured to wait for the flag using a completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int stu300_await_event(struct stu300_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) enum stu300_event mr_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Is it already here? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_lock_irq(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev->cmd_err = STU300_ERROR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev->cmd_event = mr_event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) init_completion(&dev->cmd_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Turn on the I2C interrupt for current operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) stu300_irq_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Unlock the command block and wait for the event to occur */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spin_unlock_irq(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) STU300_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "wait_for_completion_interruptible_timeout()"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "returned %d waiting for event %04x\n", ret, mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (mr_event != STU300_EVENT_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(&dev->pdev->dev, "controller "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "timed out waiting for event %d, reinit "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "hardware\n", mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (void) stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (dev->cmd_err != STU300_ERROR_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (mr_event != STU300_EVENT_6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&dev->pdev->dev, "controller "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "error (await_event) %d waiting for event %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "reinit hardware\n", dev->cmd_err, mr_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (void) stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * Waits for the busy bit to go low by repeated polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BUSY_RELEASE_ATTEMPTS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int stu300_wait_while_busy(struct stu300_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) timeout = jiffies + STU300_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) while (!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* Is not busy? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((stu300_r8(dev->virtbase + I2C_SR1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) I2C_SR1_BUSY_IND) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(&dev->pdev->dev, "transaction timed out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "waiting for device to be free (not busy). "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "Attempt: %d\n", i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&dev->pdev->dev, "base address = "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "0x%p, reinit hardware\n", dev->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (void) stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(&dev->pdev->dev, "giving up after %d attempts "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct stu300_clkset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct stu300_clkset stu300_clktable[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 0, 0xFFU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 2500000, I2C_OAR2_FR_25_10MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 10000000, I2C_OAR2_FR_10_1667MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 16670000, I2C_OAR2_FR_1667_2667MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 26670000, I2C_OAR2_FR_2667_40MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 40000000, I2C_OAR2_FR_40_5333MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 53330000, I2C_OAR2_FR_5333_66MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 66000000, I2C_OAR2_FR_66_80MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 80000000, I2C_OAR2_FR_80_100MHZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 100000000, 0xFFU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Locate the appropriate clock setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) stu300_clktable[i].rate < clkrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (stu300_clktable[i].setting == 0xFFU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(&dev->pdev->dev, "too %s clock rate requested "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "(%lu Hz).\n", i ? "high" : "low", clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) stu300_wr8(stu300_clktable[i].setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dev->virtbase + I2C_OAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Fast Mode I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) val = ((clkrate/dev->speed) - 9)/3 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Standard Mode I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val = ((clkrate/dev->speed) - 7)/2 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* According to spec the divider must be > 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (val < 0x002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* We have 12 bits clock divider only! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (val & 0xFFFFF000U) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* CC6..CC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev->virtbase + I2C_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "Fast Mode I2C\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* CC6..CC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) stu300_wr8((val & I2C_CCR_CC_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev->virtbase + I2C_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_dbg(&dev->pdev->dev, "set clock divider to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "0x%08x, Standard Mode I2C\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* CC11..CC7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stu300_wr8(((val >> 7) & 0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev->virtbase + I2C_ECCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int stu300_init_hw(struct stu300_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) unsigned long clkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Disable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) stu300_wr8(0x00, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Set own address to some default value (0x00).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * We do not support slave mode anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * The I2C controller only operates properly in 26 MHz but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * program this driver as if we didn't know. This will also set the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * high bits of the own address to zero as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * There is no known hardware issue with running in 13 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * However, speeds over 200 kHz are not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) clkrate = clk_get_rate(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = stu300_set_clk(dev, clkrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * Enable block, do it TWICE (hardware glitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * Setting bit 7 can enable DDC mode. (Not used currently.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Make a dummy read of the status register SR1 & SR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dummy = stu300_r8(dev->virtbase + I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dummy = stu300_r8(dev->virtbase + I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Send slave address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int stu300_send_address(struct stu300_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct i2c_msg *msg, int resend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* This is probably how 10 bit addresses look */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) I2C_DR_D_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* This is the direction bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) val |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val = i2c_8bit_addr_from_msg(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (resend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_dbg(&dev->pdev->dev, "read resend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_dbg(&dev->pdev->dev, "write resend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) stu300_wr8(val, dev->virtbase + I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* For 10bit addressing, await 10bit request (EVENT 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = stu300_await_event(dev, STU300_EVENT_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * The slave device wants a 10bit address, send the rest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * of the bits (the LSBits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) val = msg->addr & I2C_DR_D_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* This clears "event 9" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) stu300_wr8(val, dev->virtbase + I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* FIXME: Why no else here? two events for 10bit?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * Await event 6 (normal) or event 9 (10bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (resend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(&dev->pdev->dev, "await event 6\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = stu300_await_event(dev, STU300_EVENT_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * Clear any pending EVENT 6 no matter what happened during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * await_event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val = stu300_r8(dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val |= I2C_CR_PERIPHERAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int stu300_xfer_msg(struct i2c_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct i2c_msg *msg, int stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int attempts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct stu300_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) clk_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Remove this if (0) to trace each and every message. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "flags: 0x%04x, stop: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) msg->addr, msg->len, msg->flags, stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * For some reason, sending the address sometimes fails when running
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * on the 13 MHz clock. No interrupt arrives. This is a work around,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * which tries to restart and send the address up to 10 times before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * really giving up. Usually 5 to 8 attempts are enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (attempts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(&dev->pdev->dev, "wait while busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Check that the bus is free, or wait until some timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ret = stu300_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (attempts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(&dev->pdev->dev, "re-int hw\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * According to ST, there is no problem if the clock is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * changed between 13 and 26 MHz during a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Send a start condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cr = I2C_CR_PERIPHERAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Setting the START bit puts the block in master mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!(msg->flags & I2C_M_NOSTART))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) cr |= I2C_CR_START_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if ((msg->flags & I2C_M_RD) && (msg->len > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* On read more than 1 byte, we need ack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) cr |= I2C_CR_ACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Check that it gets through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!(msg->flags & I2C_M_NOSTART)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (attempts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_dbg(&dev->pdev->dev, "send start event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = stu300_start_and_await_event(dev, cr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) STU300_EVENT_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (attempts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_dbg(&dev->pdev->dev, "send address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* Send address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ret = stu300_send_address(dev, msg, attempts != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) attempts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_dbg(&dev->pdev->dev, "failed sending address, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "retrying. Attempt: %d msg_index: %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) attempts, dev->msg_index, dev->msg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_dbg(&dev->pdev->dev, "managed to get address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "through after %d attempts\n", attempts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "to resend address.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) NUM_ADDR_RESEND_ATTEMPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (msg->flags & I2C_M_RD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* READ: we read the actual bytes one at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (i == msg->len-1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Disable ACK and set STOP condition before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * reading last byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = I2C_CR_PERIPHERAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) val |= I2C_CR_STOP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) stu300_wr8(val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Wait for this byte... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = stu300_await_event(dev, STU300_EVENT_7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* This clears event 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* WRITE: we send the actual bytes one at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Write the byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) stu300_wr8(msg->buf[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev->virtbase + I2C_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Check status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = stu300_await_event(dev, STU300_EVENT_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Next write to DR will clear event 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&dev->pdev->dev, "error awaiting "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "event 8 (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Check NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!(msg->flags & I2C_M_IGNORE_NAK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (stu300_r8(dev->virtbase + I2C_SR2) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) I2C_SR2_AF_IND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&dev->pdev->dev, "I2C payload "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "send returned NAK!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Send stop condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) val = I2C_CR_PERIPHERAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) val |= I2C_CR_STOP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) stu300_wr8(val, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Check that the bus is free, or wait until some timeout occurs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = stu300_wait_while_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_err(&dev->pdev->dev, "timeout waiting for transfer "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "to commence.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto exit_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Dummy read status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) val = stu300_r8(dev->virtbase + I2C_SR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) val = stu300_r8(dev->virtbase + I2C_SR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) exit_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Disable controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) stu300_wr8(0x00, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) clk_disable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct stu300_dev *dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev->msg_len = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * Another driver appears to send stop for each message,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * here we only do that for the last message. Possibly some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * peripherals require this behaviour, then their drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * have to send single messages in order to get "stop" for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * each message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev->msg_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) num = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* TODO: implement polling for this case if need be. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) WARN(1, "%s: atomic transfers not implemented\n", dev_name(&adap->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static u32 stu300_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* This is the simplest thing you can think of... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct i2c_algorithm stu300_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .master_xfer = stu300_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .master_xfer_atomic = stu300_xfer_todo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .functionality = stu300_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct i2c_adapter_quirks stu300_quirks = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .flags = I2C_AQ_NO_ZERO_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int stu300_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct stu300_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int bus_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) bus_nr = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (IS_ERR(dev->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return PTR_ERR(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev->virtbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "base %p\n", bus_nr, dev->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (IS_ERR(dev->virtbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return PTR_ERR(dev->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev->speed = scl_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) clk_prepare_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) clk_disable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_err(&dev->pdev->dev, "error initializing hardware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* IRQ event handling initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) spin_lock_init(&dev->cmd_issue_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev->cmd_event = STU300_EVENT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev->cmd_err = STU300_ERROR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) adap = &dev->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* DDC class but actually often used for more generic I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) adap->class = I2C_CLASS_DEPRECATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) sizeof(adap->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) adap->nr = bus_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) adap->algo = &stu300_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) adap->quirks = &stu300_quirks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) i2c_set_adapdata(adap, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* i2c device drivers may be active on return from add_adapter() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = i2c_add_numbered_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev->virtbase, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int stu300_suspend(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct stu300_dev *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* Turn off everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) stu300_wr8(0x00, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int stu300_resume(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct stu300_dev *dev = dev_get_drvdata(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) clk_enable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = stu300_init_hw(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) clk_disable(dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_err(device, "error re-initializing hardware.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define STU300_I2C_PM (&stu300_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define STU300_I2C_PM NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int stu300_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct stu300_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) i2c_del_adapter(&dev->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Turn off everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) stu300_wr8(0x00, dev->virtbase + I2C_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const struct of_device_id stu300_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { .compatible = "st,ddci2c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_DEVICE_TABLE(of, stu300_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static struct platform_driver stu300_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .name = NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .pm = STU300_I2C_PM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .of_match_table = stu300_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .probe = stu300_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .remove = stu300_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int __init stu300_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return platform_driver_register(&stu300_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static void __exit stu300_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) platform_driver_unregister(&stu300_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * The systems using this bus often have very basic devices such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * as regulators on the I2C bus, so this needs to be loaded early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Therefore it is registered in the subsys_initcall().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) subsys_initcall(stu300_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) module_exit(stu300_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) MODULE_ALIAS("platform:" NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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