^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for STMicroelectronics STM32F7 I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * reference manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Please see below a link to the documentation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) M'boumba Cedric Madianga 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This driver is based on i2c-stm32f4.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c-smbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "i2c-stm32.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* STM32F7 I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STM32F7_I2C_CR1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STM32F7_I2C_CR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STM32F7_I2C_OAR1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STM32F7_I2C_OAR2 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STM32F7_I2C_PECR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STM32F7_I2C_TIMINGR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STM32F7_I2C_ISR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STM32F7_I2C_ICR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STM32F7_I2C_RXDR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STM32F7_I2C_TXDR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* STM32F7 I2C control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STM32F7_I2C_CR1_PECEN BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STM32F7_I2C_CR1_SMBHEN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STM32F7_I2C_CR1_WUPEN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STM32F7_I2C_CR1_SBC BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STM32F7_I2C_CR1_ANFOFF BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STM32F7_I2C_CR1_ERRIE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STM32F7_I2C_CR1_TCIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STM32F7_I2C_CR1_STOPIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define STM32F7_I2C_CR1_NACKIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define STM32F7_I2C_CR1_ADDRIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define STM32F7_I2C_CR1_RXIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define STM32F7_I2C_CR1_TXIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define STM32F7_I2C_CR1_PE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) | STM32F7_I2C_CR1_TCIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) | STM32F7_I2C_CR1_STOPIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) | STM32F7_I2C_CR1_NACKIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) | STM32F7_I2C_CR1_RXIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) | STM32F7_I2C_CR1_TXIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) | STM32F7_I2C_CR1_STOPIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) | STM32F7_I2C_CR1_NACKIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) | STM32F7_I2C_CR1_RXIE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) | STM32F7_I2C_CR1_TXIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* STM32F7 I2C control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STM32F7_I2C_CR2_PECBYTE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STM32F7_I2C_CR2_RELOAD BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STM32F7_I2C_CR2_NACK BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STM32F7_I2C_CR2_STOP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STM32F7_I2C_CR2_START BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STM32F7_I2C_CR2_HEAD10R BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STM32F7_I2C_CR2_ADD10 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STM32F7_I2C_CR2_RD_WRN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) STM32F7_I2C_CR2_SADD10_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* STM32F7 I2C Own Address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STM32F7_I2C_OAR1_OA1EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) STM32F7_I2C_OAR1_OA1_10_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) | STM32F7_I2C_OAR1_OA1_10_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | STM32F7_I2C_OAR1_OA1EN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | STM32F7_I2C_OAR1_OA1MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* STM32F7 I2C Own Address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define STM32F7_I2C_OAR2_OA2EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) | STM32F7_I2C_OAR2_OA2_7_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) | STM32F7_I2C_OAR2_OA2EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* STM32F7 I2C Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define STM32F7_I2C_ISR_DIR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define STM32F7_I2C_ISR_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define STM32F7_I2C_ISR_PECERR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define STM32F7_I2C_ISR_ARLO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define STM32F7_I2C_ISR_BERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define STM32F7_I2C_ISR_TCR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STM32F7_I2C_ISR_TC BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define STM32F7_I2C_ISR_STOPF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define STM32F7_I2C_ISR_NACKF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define STM32F7_I2C_ISR_ADDR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define STM32F7_I2C_ISR_RXNE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define STM32F7_I2C_ISR_TXIS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define STM32F7_I2C_ISR_TXE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* STM32F7 I2C Interrupt Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define STM32F7_I2C_ICR_PECCF BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define STM32F7_I2C_ICR_ARLOCF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define STM32F7_I2C_ICR_BERRCF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define STM32F7_I2C_ICR_STOPCF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define STM32F7_I2C_ICR_NACKCF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define STM32F7_I2C_ICR_ADDRCF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* STM32F7 I2C Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define STM32F7_I2C_MAX_LEN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define STM32F7_I2C_DMA_LEN_MIN 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) STM32F7_SLAVE_HOSTNOTIFY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) STM32F7_SLAVE_7_10_BITS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) STM32F7_SLAVE_7_BITS_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) STM32F7_I2C_MAX_SLAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define STM32F7_I2C_DNF_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define STM32F7_I2C_DNF_MAX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define STM32F7_PRESC_MAX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define STM32F7_SCLDEL_MAX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define STM32F7_SDADEL_MAX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define STM32F7_SCLH_MAX BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define STM32F7_SCLL_MAX BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * struct stm32f7_i2c_regs - i2c f7 registers backup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @cr1: Control register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @cr2: Control register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @oar1: Own address 1 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @oar2: Own address 2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @tmgr: Timing register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct stm32f7_i2c_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 oar1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 oar2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 tmgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * struct stm32f7_i2c_spec - private i2c specification timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @rate: I2C bus speed (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @fall_max: Max fall time of both SDA and SCL signals (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @rise_max: Max rise time of both SDA and SCL signals (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @hddat_min: Min data hold time (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @vddat_max: Max data valid time (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @sudat_min: Min data setup time (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @l_min: Min low period of the SCL clock (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @h_min: Min high period of the SCL clock (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct stm32f7_i2c_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 fall_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 rise_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 hddat_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 vddat_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 sudat_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 l_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 h_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * struct stm32f7_i2c_setup - private I2C timing setup parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @speed_freq: I2C speed frequency (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @clock_src: I2C clock source frequency (Hz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @rise_time: Rise time (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @fall_time: Fall time (ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @dnf: Digital filter coefficient (0-16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @analog_filter: Analog filter delay (On/Off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct stm32f7_i2c_setup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 speed_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 clock_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 rise_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 fall_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 dnf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bool analog_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 fmp_clr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * struct stm32f7_i2c_timings - private I2C output parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @node: List entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @presc: Prescaler value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @scldel: Data setup time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @sdadel: Data hold time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @sclh: SCL high period (master mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @scll: SCL low period (master mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct stm32f7_i2c_timings {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 scldel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u8 sdadel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 sclh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u8 scll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * struct stm32f7_i2c_msg - client specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @addr: 8-bit or 10-bit slave addr, including r/w bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @count: number of bytes to be transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @buf: data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @result: result of the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @stop: last I2C msg to be sent, i.e. STOP to be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @smbus: boolean to know if the I2C IP is used in SMBus mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @size: type of SMBus protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @read_write: direction of SMBus protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * SMBus block read and SMBus block write - block read process call protocols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * contain a maximum of 32 bytes of data + byte command + byte count + PEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This buffer has to be 32-bit aligned to be compliant with memory address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * register in DMA mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct stm32f7_i2c_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) bool stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) char read_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * struct stm32f7_i2c_dev - private data of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @adap: I2C adapter for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @dev: device for this controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @base: virtual memory area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @complete: completion of I2C message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @clk: hw i2c clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @bus_rate: I2C clock frequency of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @msg: Pointer to data to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @msg_num: number of I2C messages to be executed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @msg_id: message identifiant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @f7_msg: customized i2c msg for driver usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @setup: I2C timing input setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @timing: I2C computed timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @slave: list of slave devices registered on the I2C bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @slave_running: slave device currently used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @backup_regs: backup of i2c controller registers (for suspend/resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @slave_dir: transfer direction for the current slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @master_mode: boolean to know in which mode the I2C is running (master or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @dma: dma data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @use_dma: boolean to know if dma is used in the current transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @fmp_sreg: register address for setting Fast Mode Plus bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @fmp_creg: register address for clearing Fast Mode Plus bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @fmp_mask: mask for Fast Mode Plus bits in set register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @wakeup_src: boolean to know if the device is a wakeup source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @smbus_mode: states that the controller is configured in SMBus mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @host_notify_client: SMBus host-notify client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct stm32f7_i2c_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct i2c_adapter adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct completion complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int bus_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int msg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int msg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct stm32f7_i2c_msg f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct stm32f7_i2c_setup setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct stm32f7_i2c_timings timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct i2c_client *slave_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct stm32f7_i2c_regs backup_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 slave_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bool master_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct stm32_i2c_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bool use_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 fmp_sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 fmp_creg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 fmp_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bool wakeup_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bool smbus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct i2c_client *host_notify_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * All these values are coming from I2C Specification, Version 6.0, 4th of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * April 2014.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * and Fast-mode Plus I2C-bus devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .rate = I2C_MAX_STANDARD_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .fall_max = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .rise_max = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .hddat_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .vddat_max = 3450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .sudat_min = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .l_min = 4700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .h_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .rate = I2C_MAX_FAST_MODE_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .fall_max = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .rise_max = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .hddat_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .vddat_max = 900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .sudat_min = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .l_min = 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .h_min = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .fall_max = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .rise_max = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .hddat_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .vddat_max = 450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .sudat_min = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .l_min = 500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .h_min = 260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct stm32f7_i2c_setup stm32f7_setup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .dnf = STM32F7_I2C_DNF_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct stm32f7_i2c_setup stm32mp15_setup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .dnf = STM32F7_I2C_DNF_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .fmp_clr_offset = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel_relaxed(readl_relaxed(reg) | mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel_relaxed(readl_relaxed(reg) & ~mask, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (rate <= stm32f7_i2c_specs[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return &stm32f7_i2c_specs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define RATE_MIN(rate) ((rate) * 8 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct stm32f7_i2c_setup *setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct stm32f7_i2c_timings *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct stm32f7_i2c_spec *specs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 p_prev = STM32F7_PRESC_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) setup->clock_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 clk_error_prev = i2cbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 tsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 af_delay_min, af_delay_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 dnf_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 clk_min, clk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int sdadel_min, sdadel_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int scldel_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct stm32f7_i2c_timings *v, *_v, *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct list_head solutions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u16 p, l, a, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) specs = stm32f7_get_specs(setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (specs == ERR_PTR(-EINVAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if ((setup->rise_time > specs->rise_max) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) (setup->fall_time > specs->fall_max)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) setup->rise_time, specs->rise_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) setup->fall_time, specs->fall_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (setup->dnf > STM32F7_I2C_DNF_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "DNF out of bound %d/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) setup->dnf, STM32F7_I2C_DNF_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Analog and Digital Filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) af_delay_min =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) (setup->analog_filter ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) af_delay_max =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) (setup->analog_filter ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dnf_delay = setup->dnf * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sdadel_min = specs->hddat_min + setup->fall_time -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) af_delay_min - (setup->dnf + 3) * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sdadel_max = specs->vddat_max - setup->rise_time -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) af_delay_max - (setup->dnf + 4) * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) scldel_min = setup->rise_time + specs->sudat_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (sdadel_min < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sdadel_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (sdadel_max < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sdadel_max = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sdadel_min, sdadel_max, scldel_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) INIT_LIST_HEAD(&solutions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Compute possible values for PRESC, SCLDEL and SDADEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) for (p = 0; p < STM32F7_PRESC_MAX; p++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 scldel = (l + 1) * (p + 1) * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (scldel < scldel_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 sdadel = (a * (p + 1) + 1) * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (((sdadel >= sdadel_min) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) (sdadel <= sdadel_max)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (p != p_prev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) v = kmalloc(sizeof(*v), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) v->presc = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) v->scldel = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) v->sdadel = a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) p_prev = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) list_add_tail(&v->node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &solutions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (p_prev == p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (list_empty(&solutions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(i2c_dev->dev, "no Prescaler solution\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) tsync = af_delay_min + dnf_delay + (2 * i2cclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) s = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clk_min = NSEC_PER_SEC / setup->speed_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Among Prescaler possibilities discovered above figures out SCL Low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * and High Period. Provided:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * - SCL Low Period has to be higher than SCL Clock Low Period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * defined by I2C Specification. I2C Clock has to be lower than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * (SCL Low Period - Analog/Digital filters) / 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * - SCL High Period has to be lower than SCL Clock High Period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * defined by I2C Specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * - I2C Clock has to be lower than SCL High Period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) list_for_each_entry(v, &solutions, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 prescaler = (v->presc + 1) * i2cclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) for (l = 0; l < STM32F7_SCLL_MAX; l++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 tscl_l = (l + 1) * prescaler + tsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if ((tscl_l < specs->l_min) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) (i2cclk >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ((tscl_l - af_delay_min - dnf_delay) / 4))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) for (h = 0; h < STM32F7_SCLH_MAX; h++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 tscl_h = (h + 1) * prescaler + tsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 tscl = tscl_l + tscl_h +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) setup->rise_time + setup->fall_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if ((tscl >= clk_min) && (tscl <= clk_max) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (tscl_h >= specs->h_min) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) (i2cclk < tscl_h)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int clk_error = tscl - i2cbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (clk_error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) clk_error = -clk_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (clk_error < clk_error_prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_error_prev = clk_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) v->scll = l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) v->sclh = h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) s = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev_err(i2c_dev->dev, "no solution at all\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) output->presc = s->presc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) output->scldel = s->scldel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) output->sdadel = s->sdadel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) output->scll = s->scll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) output->sclh = s->sclh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_dbg(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) output->presc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) output->scldel, output->sdadel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) output->scll, output->sclh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Release list and memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) list_for_each_entry_safe(v, _v, &solutions, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) list_del(&v->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) kfree(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static u32 stm32f7_get_lower_rate(u32 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int i = ARRAY_SIZE(stm32f7_i2c_specs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (stm32f7_i2c_specs[i].rate < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return stm32f7_i2c_specs[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct stm32f7_i2c_setup *setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct i2c_timings timings, *t = &timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) t->scl_rise_ns = i2c_dev->setup.rise_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) t->scl_fall_ns = i2c_dev->setup.fall_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) i2c_parse_fw_timings(i2c_dev->dev, t, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) setup->speed_freq = t->bus_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) i2c_dev->setup.rise_time = t->scl_rise_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) i2c_dev->setup.fall_time = t->scl_fall_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) setup->clock_src = clk_get_rate(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!setup->clock_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(i2c_dev->dev, "clock rate is 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) &i2c_dev->timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "failed to compute I2C timings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) setup->speed_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) stm32f7_get_lower_rate(setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_warn(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "downgrade I2C Speed Freq to (%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) setup->speed_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) } while (ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) setup->speed_freq, setup->clock_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) setup->rise_time, setup->fall_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (setup->analog_filter ? "On" : "Off"), setup->dnf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) i2c_dev->bus_rate = setup->speed_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static void stm32f7_i2c_dma_callback(void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct device *dev = dma->chan_using->device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) stm32f7_i2c_disable_dma_req(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) complete(&dma->dma_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct stm32f7_i2c_timings *t = &i2c_dev->timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 timing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Timing settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (i2c_dev->setup.analog_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) STM32F7_I2C_CR1_ANFOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) STM32F7_I2C_CR1_ANFOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Program the Digital Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) STM32F7_I2C_CR1_DNF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) STM32F7_I2C_CR1_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (f7_msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) f7_msg->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (f7_msg->count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) f7_msg->count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Flush RX buffer has no data is expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) readb_relaxed(base + STM32F7_I2C_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u32 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (i2c_dev->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) f7_msg->count -= STM32F7_I2C_MAX_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cr2 &= ~STM32F7_I2C_CR2_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u8 *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * data received inform us how many data will follow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) stm32f7_i2c_read_rx_data(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * Update NBYTES with the value read to continue the transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) val = f7_msg->buf - sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) f7_msg->count = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_info(i2c_dev->dev, "Trying to recover bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) STM32F7_I2C_CR1_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) stm32f7_i2c_hw_config(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) !(status & STM32F7_I2C_ISR_BUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_info(i2c_dev->dev, "bus busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct i2c_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 cr1, cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) f7_msg->addr = msg->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) f7_msg->buf = msg->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) f7_msg->count = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) f7_msg->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Set transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) cr2 |= STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (msg->flags & I2C_M_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) cr2 |= STM32F7_I2C_CR2_ADD10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Set nb bytes to transfer and reload if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) cr2 |= STM32F7_I2C_CR2_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Enable NACK, STOP, error and transfer complete interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Clear DMA req and TX/RX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Configure DMA or enable RX/TX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) i2c_dev->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) msg->flags & I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) f7_msg->count, f7_msg->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) stm32f7_i2c_dma_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) i2c_dev->use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev_warn(i2c_dev->dev, "can't use DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (!i2c_dev->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) cr1 |= STM32F7_I2C_CR1_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) cr1 |= STM32F7_I2C_CR1_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (msg->flags & I2C_M_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) cr1 |= STM32F7_I2C_CR1_RXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cr1 |= STM32F7_I2C_CR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Configure Start/Repeated Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) cr2 |= STM32F7_I2C_CR2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) i2c_dev->master_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Write configurations registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) writel_relaxed(cr1, base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) writel_relaxed(cr2, base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned short flags, u8 command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct device *dev = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 cr1, cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) f7_msg->result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) reinit_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Set transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (f7_msg->read_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) cr2 |= STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Set slave address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) f7_msg->smbus_buf[0] = command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) switch (f7_msg->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case I2C_SMBUS_QUICK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) f7_msg->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (f7_msg->read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) f7_msg->stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) f7_msg->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) f7_msg->smbus_buf[1] = data->byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (f7_msg->read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) f7_msg->stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) f7_msg->count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) f7_msg->smbus_buf[1] = data->word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) f7_msg->smbus_buf[2] = data->word >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (f7_msg->read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) f7_msg->stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) !data->block[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_err(dev, "Invalid block write size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) data->block[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) f7_msg->count = data->block[0] + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (i = 1; i < f7_msg->count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) f7_msg->smbus_buf[i] = data->block[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) f7_msg->stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) f7_msg->count = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) f7_msg->smbus_buf[1] = data->word & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) f7_msg->smbus_buf[2] = data->word >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) f7_msg->read_write = I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) f7_msg->stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dev_err(dev, "Invalid block write size %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) data->block[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) f7_msg->count = data->block[0] + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) for (i = 1; i < f7_msg->count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) f7_msg->smbus_buf[i] = data->block[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) f7_msg->read_write = I2C_SMBUS_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case I2C_SMBUS_I2C_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* Rely on emulated i2c transfer (through master_xfer) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) f7_msg->buf = f7_msg->smbus_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Configure PEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) cr1 |= STM32F7_I2C_CR1_PECEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cr2 |= STM32F7_I2C_CR2_PECBYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (!f7_msg->read_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) f7_msg->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) cr1 &= ~STM32F7_I2C_CR1_PECEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Set number of bytes to be transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* Enable NACK, STOP, error and transfer complete interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Clear DMA req and TX/RX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Configure DMA or enable RX/TX interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) i2c_dev->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) cr2 & STM32F7_I2C_CR2_RD_WRN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) f7_msg->count, f7_msg->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) stm32f7_i2c_dma_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) i2c_dev->use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev_warn(i2c_dev->dev, "can't use DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!i2c_dev->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (cr2 & STM32F7_I2C_CR2_RD_WRN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) cr1 |= STM32F7_I2C_CR1_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) cr1 |= STM32F7_I2C_CR1_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (cr2 & STM32F7_I2C_CR2_RD_WRN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) cr1 |= STM32F7_I2C_CR1_RXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cr1 |= STM32F7_I2C_CR1_TXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Set Start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) cr2 |= STM32F7_I2C_CR2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) i2c_dev->master_mode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Write configurations registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) writel_relaxed(cr1, base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) writel_relaxed(cr2, base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) u32 cr1, cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Set transfer direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cr2 |= STM32F7_I2C_CR2_RD_WRN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) switch (f7_msg->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) f7_msg->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) f7_msg->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) cr2 |= STM32F7_I2C_CR2_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) f7_msg->buf = f7_msg->smbus_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) f7_msg->stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Add one byte for PEC if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (cr1 & STM32F7_I2C_CR1_PECEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) f7_msg->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* Set number of bytes to be transferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * Configure RX/TX interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cr1 |= STM32F7_I2C_CR1_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * Configure DMA or enable RX/TX interrupt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * dma as we don't know in advance how many data will be received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) i2c_dev->use_dma = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) cr2 & STM32F7_I2C_CR2_RD_WRN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) f7_msg->count, f7_msg->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) stm32f7_i2c_dma_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) i2c_dev->use_dma = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_warn(i2c_dev->dev, "can't use DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (!i2c_dev->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) cr1 |= STM32F7_I2C_CR1_RXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) cr1 |= STM32F7_I2C_CR1_RXDMAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Configure Repeated Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) cr2 |= STM32F7_I2C_CR2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* Write configurations registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) writel_relaxed(cr1, base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) writel_relaxed(cr2, base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u8 count, internal_pec, received_pec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) switch (f7_msg->size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) received_pec = f7_msg->smbus_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) received_pec = f7_msg->smbus_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) count = f7_msg->smbus_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) received_pec = f7_msg->smbus_buf[count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (internal_pec != received_pec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) internal_pec, received_pec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (slave->flags & I2C_CLIENT_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * For 10-bit addr, addcode = 11110XY with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * X = Bit 9 of slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Y = Bit 8 of slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) addr = slave->addr >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) addr |= 0x78;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (addr == addcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) addr = slave->addr & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (addr == addcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct i2c_client *slave = i2c_dev->slave_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) if (i2c_dev->slave_dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Notify i2c slave that new read transfer is starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * Disable slave TX config in case of I2C combined message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * (I2C Write followed by I2C Read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) mask = STM32F7_I2C_CR2_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) STM32F7_I2C_CR1_TCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Enable TX empty, STOP, NACK interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) STM32F7_I2C_CR1_TXIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Write 1st data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) writel_relaxed(value, base + STM32F7_I2C_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Notify i2c slave that new write transfer is starting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* Set reload mode to be able to ACK/NACK each received byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mask = STM32F7_I2C_CR2_RELOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * Set STOP, NACK, RX empty and transfer complete interrupts.*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * Set Slave Byte Control to be able to ACK/NACK each data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * byte received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) STM32F7_I2C_CR1_TCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u32 isr, addcode, dir, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dir = isr & STM32F7_I2C_ISR_DIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) i2c_dev->slave_running = i2c_dev->slave[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) i2c_dev->slave_dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Start I2C slave processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) stm32f7_i2c_slave_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Clear ADDR flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) mask = STM32F7_I2C_ICR_ADDRCF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) writel_relaxed(mask, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct i2c_client *slave, int *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (i2c_dev->slave[i] == slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) *id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct i2c_client *slave, int *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) struct device *dev = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) *id = STM32F7_SLAVE_HOSTNOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) (slave->flags & I2C_CLIENT_TEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!i2c_dev->slave[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (i2c_dev->slave[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) int i, busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (i2c_dev->slave[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) busy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return i == busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) u32 cr2, status, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* Slave transmitter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (status & STM32F7_I2C_ISR_TXIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) i2c_slave_event(i2c_dev->slave_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) I2C_SLAVE_READ_PROCESSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* Write data byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) writel_relaxed(val, base + STM32F7_I2C_TXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Transfer Complete Reload for Slave receiver mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * Read data byte then set NBYTES to receive next byte or NACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * the current received byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = i2c_slave_event(i2c_dev->slave_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) I2C_SLAVE_WRITE_RECEIVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) cr2 |= STM32F7_I2C_CR2_NBYTES(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) mask = STM32F7_I2C_CR2_NACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* NACK received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (status & STM32F7_I2C_ISR_NACKF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* STOP received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (status & STM32F7_I2C_ISR_STOPF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (i2c_dev->slave_dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * Flush TX buffer in order to not used the byte in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * TXDR for the next transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mask = STM32F7_I2C_ISR_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* Clear STOP flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* Notify i2c slave that a STOP flag has been detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) i2c_dev->slave_running = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* Address match received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (status & STM32F7_I2C_ISR_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) stm32f7_i2c_slave_addr(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct stm32f7_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) u32 status, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) int ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* Check if the interrupt if for a slave device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (!i2c_dev->master_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret = stm32f7_i2c_slave_isr_event(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Tx empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (status & STM32F7_I2C_ISR_TXIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) stm32f7_i2c_write_tx_data(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* RX not empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (status & STM32F7_I2C_ISR_RXNE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) stm32f7_i2c_read_rx_data(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* NACK received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (status & STM32F7_I2C_ISR_NACKF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) __func__, f7_msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (i2c_dev->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) stm32f7_i2c_disable_dma_req(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) f7_msg->result = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* STOP detection flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (status & STM32F7_I2C_ISR_STOPF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (stm32f7_i2c_is_slave_registered(i2c_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) mask = STM32F7_I2C_XFER_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) mask = STM32F7_I2C_ALL_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) stm32f7_i2c_disable_irq(i2c_dev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* Clear STOP flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (i2c_dev->use_dma && !f7_msg->result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) i2c_dev->master_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Transfer complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (status & STM32F7_I2C_ISR_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (f7_msg->stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) mask = STM32F7_I2C_CR2_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) } else if (i2c_dev->use_dma && !f7_msg->result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ret = IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) } else if (f7_msg->smbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) stm32f7_i2c_smbus_rep_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) i2c_dev->msg_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) i2c_dev->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (status & STM32F7_I2C_ISR_TCR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (f7_msg->smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) stm32f7_i2c_smbus_reload(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) stm32f7_i2c_reload(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct stm32f7_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * Wait for dma transfer completion before sending next message or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * notity the end of xfer to the client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) stm32f7_i2c_disable_dma_req(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) f7_msg->result = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (status & STM32F7_I2C_ISR_TC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (f7_msg->smbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) stm32f7_i2c_smbus_rep_start(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) i2c_dev->msg_id++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) i2c_dev->msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) i2c_dev->master_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct stm32f7_i2c_dev *i2c_dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct device *dev = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* Bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) if (status & STM32F7_I2C_ISR_BERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_err(dev, "<%s>: Bus error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) stm32f7_i2c_release_bus(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) f7_msg->result = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* Arbitration loss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (status & STM32F7_I2C_ISR_ARLO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) f7_msg->result = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (status & STM32F7_I2C_ISR_PECERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) dev_err(dev, "<%s>: PEC error in reception\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) f7_msg->result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (!i2c_dev->slave_running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (stm32f7_i2c_is_slave_registered(i2c_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) mask = STM32F7_I2C_XFER_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) mask = STM32F7_I2C_ALL_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) stm32f7_i2c_disable_irq(i2c_dev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* Disable dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (i2c_dev->use_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) stm32f7_i2c_disable_dma_req(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) i2c_dev->master_mode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) complete(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct i2c_msg msgs[], int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) i2c_dev->msg = msgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) i2c_dev->msg_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) i2c_dev->msg_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) f7_msg->smbus = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ret = stm32f7_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) stm32f7_i2c_xfer_msg(i2c_dev, msgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) time_left = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) i2c_dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ret = f7_msg->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) * It is possible that some unsent data have already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * written into TXDR. To avoid sending old data in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) * further transfer, flush TXDR in case of any error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) writel_relaxed(STM32F7_I2C_ISR_TXE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (!time_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) i2c_dev->msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (i2c_dev->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) stm32f7_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) pm_runtime_mark_last_busy(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pm_runtime_put_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return (ret < 0) ? ret : num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) unsigned short flags, char read_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u8 command, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) union i2c_smbus_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct stm32_i2c_dma *dma = i2c_dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct device *dev = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) f7_msg->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) f7_msg->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) f7_msg->read_write = read_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) f7_msg->smbus = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ret = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) ret = stm32f7_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) timeout = wait_for_completion_timeout(&i2c_dev->complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) i2c_dev->adap.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ret = f7_msg->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) * It is possible that some unsent data have already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * written into TXDR. To avoid sending old data in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * further transfer, flush TXDR in case of any error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) writel_relaxed(STM32F7_I2C_ISR_TXE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) i2c_dev->base + STM32F7_I2C_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (i2c_dev->use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dmaengine_terminate_all(dma->chan_using);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) stm32f7_i2c_wait_free_bus(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* Check PEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (read_write && size != I2C_SMBUS_QUICK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) case I2C_SMBUS_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) case I2C_SMBUS_BYTE_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) data->byte = f7_msg->smbus_buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) case I2C_SMBUS_WORD_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case I2C_SMBUS_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) data->word = f7_msg->smbus_buf[0] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) (f7_msg->smbus_buf[1] << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case I2C_SMBUS_BLOCK_DATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case I2C_SMBUS_BLOCK_PROC_CALL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) data->block[i] = f7_msg->smbus_buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) dev_err(dev, "Unsupported smbus transaction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) pm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) u32 mask = STM32F7_I2C_CR1_WUPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (!i2c_dev->wakeup_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) device_set_wakeup_enable(i2c_dev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) device_set_wakeup_enable(i2c_dev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) struct device *dev = i2c_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) u32 oar1, oar2, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (slave->flags & I2C_CLIENT_PEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) dev_err(dev, "SMBus PEC not supported in slave mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_err(dev, "Too much slave registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ret = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (!stm32f7_i2c_is_slave_registered(i2c_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) stm32f7_i2c_enable_wakeup(i2c_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* Slave SMBus Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) i2c_dev->slave[id] = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* Configure Own Address 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) oar1 &= ~STM32F7_I2C_OAR1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) if (slave->flags & I2C_CLIENT_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) oar1 |= STM32F7_I2C_OAR1_OA1MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) oar1 |= STM32F7_I2C_OAR1_OA1EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) i2c_dev->slave[id] = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* Configure Own Address 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) oar2 &= ~STM32F7_I2C_OAR2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) if (slave->flags & I2C_CLIENT_TEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) oar2 |= STM32F7_I2C_OAR2_OA2EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) i2c_dev->slave[id] = slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) dev_err(dev, "I2C slave id not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) goto pm_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* Enable ACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* Enable Address match interrupt, error interrupt and enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) STM32F7_I2C_CR1_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) pm_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (!stm32f7_i2c_is_slave_registered(i2c_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) stm32f7_i2c_enable_wakeup(i2c_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) WARN_ON(!i2c_dev->slave[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) mask = STM32F7_I2C_OAR1_OA1EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) } else if (id == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) mask = STM32F7_I2C_OAR2_OA2EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) i2c_dev->slave[id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) stm32f7_i2c_enable_wakeup(i2c_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) pm_runtime_mark_last_busy(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) pm_runtime_put_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) IS_ERR_OR_NULL(i2c_dev->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ret = regmap_update_bits(i2c_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) i2c_dev->fmp_sreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) i2c_dev->fmp_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) enable ? i2c_dev->fmp_mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ret = regmap_write(i2c_dev->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) enable ? i2c_dev->fmp_sreg :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) i2c_dev->fmp_creg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) i2c_dev->fmp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (IS_ERR(i2c_dev->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) &i2c_dev->fmp_sreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) i2c_dev->setup.fmp_clr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) &i2c_dev->fmp_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct i2c_adapter *adap = &i2c_dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) client = i2c_new_slave_host_notify_device(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (IS_ERR(client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return PTR_ERR(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) i2c_dev->host_notify_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* Enable SMBus Host address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) void __iomem *base = i2c_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) if (i2c_dev->host_notify_client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /* Disable SMBus Host address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) STM32F7_I2C_CR1_SMBHEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) I2C_FUNC_SMBUS_I2C_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) if (i2c_dev->smbus_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static const struct i2c_algorithm stm32f7_i2c_algo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .master_xfer = stm32f7_i2c_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .smbus_xfer = stm32f7_i2c_smbus_xfer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .functionality = stm32f7_i2c_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .reg_slave = stm32f7_i2c_reg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .unreg_slave = stm32f7_i2c_unreg_slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static int stm32f7_i2c_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct stm32f7_i2c_dev *i2c_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) const struct stm32f7_i2c_setup *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) struct i2c_adapter *adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dma_addr_t phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) int irq_error, irq_event, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (!i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (IS_ERR(i2c_dev->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return PTR_ERR(i2c_dev->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) phy_addr = (dma_addr_t)res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) irq_event = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (irq_event <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (irq_event != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) irq_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return irq_event ? : -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) irq_error = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (irq_error <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (irq_error != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) irq_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return irq_error ? : -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) "wakeup-source");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (IS_ERR(i2c_dev->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) "Failed to get controller clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) rst = devm_reset_control_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) "Error: Missing reset ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) i2c_dev->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ret = devm_request_threaded_irq(&pdev->dev, irq_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) stm32f7_i2c_isr_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) stm32f7_i2c_isr_event_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) dev_err(&pdev->dev, "Failed to request irq event %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) irq_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) pdev->name, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dev_err(&pdev->dev, "Failed to request irq error %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) irq_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) setup = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if (!setup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) dev_err(&pdev->dev, "Can't get device data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) i2c_dev->setup = *setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /* Setup Fast mode plus if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) goto clk_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) adap = &i2c_dev->adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) i2c_set_adapdata(adap, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) &res->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) adap->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) adap->timeout = 2 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) adap->retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) adap->algo = &stm32f7_i2c_algo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) adap->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) adap->dev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) init_completion(&i2c_dev->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* Init DMA config if supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) STM32F7_I2C_TXDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) STM32F7_I2C_RXDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (IS_ERR(i2c_dev->dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ret = PTR_ERR(i2c_dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* DMA support is optional, only report other errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) goto fmp_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) i2c_dev->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (i2c_dev->wakeup_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) device_set_wakeup_capable(i2c_dev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) goto clr_wakeup_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) platform_set_drvdata(pdev, i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) pm_runtime_set_autosuspend_delay(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) STM32F7_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) pm_runtime_use_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) pm_runtime_set_active(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) pm_runtime_enable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) stm32f7_i2c_hw_config(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ret = i2c_add_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) goto pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (i2c_dev->smbus_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) dev_err(i2c_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) "failed to enable SMBus Host-Notify protocol (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) goto i2c_adapter_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) pm_runtime_mark_last_busy(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) pm_runtime_put_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) i2c_adapter_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) i2c_del_adapter(adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) pm_runtime_put_noidle(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) pm_runtime_set_suspended(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) pm_runtime_dont_use_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (i2c_dev->wakeup_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) dev_pm_clear_wake_irq(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) clr_wakeup_capable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (i2c_dev->wakeup_src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) device_set_wakeup_capable(i2c_dev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (i2c_dev->dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) stm32_i2c_dma_free(i2c_dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) i2c_dev->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) fmp_clear:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) clk_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static int stm32f7_i2c_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) stm32f7_i2c_disable_smbus_host(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) i2c_del_adapter(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) pm_runtime_get_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (i2c_dev->wakeup_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) dev_pm_clear_wake_irq(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) * enforce that wakeup is disabled and that the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) * is marked as non wakeup capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) device_init_wakeup(i2c_dev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) pm_runtime_put_noidle(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) pm_runtime_disable(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) pm_runtime_set_suspended(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) pm_runtime_dont_use_autosuspend(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) if (i2c_dev->dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) stm32_i2c_dma_free(i2c_dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) i2c_dev->dma = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (!stm32f7_i2c_is_slave_registered(i2c_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) clk_disable_unprepare(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ret = clk_prepare_enable(i2c_dev->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) dev_err(dev, "failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) pm_runtime_put_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) u32 cr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ret = pm_runtime_resume_and_get(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) if (cr1 & STM32F7_I2C_CR1_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) STM32F7_I2C_CR1_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) i2c_dev->base + STM32F7_I2C_CR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) STM32F7_I2C_CR1_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) pm_runtime_put_sync(i2c_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static int stm32f7_i2c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) i2c_mark_adapter_suspended(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ret = stm32f7_i2c_regs_backup(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) i2c_mark_adapter_resumed(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) pinctrl_pm_select_sleep_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static int stm32f7_i2c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ret = pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) pinctrl_pm_select_default_state(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ret = stm32f7_i2c_regs_restore(i2c_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) i2c_mark_adapter_resumed(&i2c_dev->adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) stm32f7_i2c_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static const struct of_device_id stm32f7_i2c_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static struct platform_driver stm32f7_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .name = "stm32f7-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .of_match_table = stm32f7_i2c_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .pm = &stm32f7_i2c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .probe = stm32f7_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .remove = stm32f7_i2c_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) module_platform_driver(stm32f7_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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